When do MIPS exceptions occur IF page fault on instruction fetch misaligned memory access memory protection violation ID undefined or illegal opcode EX arithmetic exception MEM page fault on data fetch store misaligned memory access memory protection violation WB None CMSC 411 Computer Systems Architecture Lecture 6 Basic Pipelining cont CMSC 411 6 from Patterson Examples of exception handling LD IF ADD ID EX MEM WB IF ID EX MEM How is this done Answer Don t handle exceptions until the WB stage each instruction has an associated status vector that keeps track of faults any bit set in the status vector turns off register writes and memory writes in WB stage the status vector is checked and any fault is handled So since instructions reach WB in proper order faults for earlier instructions are handled before faults for later instructions Unfortunately will need to violate this later for instructions that don t reach WB in proper order WB Handle the MEM fault first then restart LD ADD IF ID EX MEM WB IF ID EX MEM WB IF fault occurs first even though LD will fault later But for precise exceptions must handle LD fault first CMSC 411 6 from Patterson CS252 S05 3 CMSC 411 6 from Patterson Commitment Complications with long instructions When an instruction is guaranteed to complete it is committed Life is easier if no instruction changes the permanent machine state before it is committed In MIPS commitment occurs at the end of the MEM stage that s why register update occurs in the stage after that Some machines muddy the state before commitment and the exception handler must do its best to restore the state that existed before the instruction started So far all MIPS instructions take 5 cycles CMSC 411 6 from Patterson 2 4 But haven t talked yet about the floating point instructions Take it on faith that floating point instructions are inherently slower than integer arithmetic instructions doubters may consult Appendix H in H P online 5 CMSC 411 6 from Patterson 6 How slow is slow Examples Some typical times latency is the number of cycles between an instruction that produces a result and one that uses it initiation interval is the number of cycles between two instructions of the same kind for example two ADD Fs If have a string of instructions ADD SUB AND OR SLLI then there are no delays in the pipeline because initiation 1 means can start one of these instructions every cycle latency 0 means that results from one instruction will be available when the next instruction needs them Instruction Latency Initiation ALU uses 0 1 Load store 1 1 ADD F SUB F 3 1 DIV F 24 25 7 CMSC 411 6 from Patterson CMSC 411 6 from Patterson 8 Functional units Fig A 31 Examples cont Suppose have a string of instructions ADD F SUB F Then initiation 1 means that can start SUB F one cycle behind ADD F But latency 3 means that this will work right only if SUB F doesn t need ADD Fs results If it does need the results then need two instructions in between ADD F and SUB F to prevent bubbles in the pipeline 9 CMSC 411 6 from Patterson Examples cont Fig A 32 MUL D ADD D L D S D IF CMSC 411 6 from Patterson 10 Hazards caused by long instructions ID M1 M2 M3 M4 M5 M6 M7 IF ID A1 A2 A3 A4 MEM WB IF ID EX MEM WB IF ID EX MEM MEM WB The floating point adder and multiplier are pipelined but the divider is not that is why the initiation interval for divide is 25 A program will run very slowly if it does too many of these It will also run slowly if the results of the divide are needed too soon WB Italics shows where data is needed blue where a result is available CMSC 411 6 from Patterson CS252 S05 11 CMSC 411 6 from Patterson 12 FP stalls from RAW hazards Fig A 33 Inst 1 L D F4 0 R2 IF MUL D F0 F4 F6 2 3 4 5 6 Long instructions cont 7 8 9 It is possible that two instructions enter the WB stage at the same time ID EX MEM WB IF ID stall M1 M2 M3 M4 M5 IF stall ID stall stall stall stall stall IF stall stall stall stall 15 16 17 ADD D ADD D F2 F0 F8 S D F2 0 R2 IF LD ID A1 A2 A3 A4 IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM DADD Inst 10 11 12 13 14 L D MUL D DADD M6 M7 MEM MEM WB WB WB ADD D stall stall A1 A2 A3 A4 MEM WB S D stall stall ID EX stall stall stall MEM A structural hazard 13 CMSC 411 6 from Patterson Long instructions cont 14 CMSC 411 6 from Patterson WAW structural hazard Instructions can finish in the wrong order 1 This can cause WAW hazards MUL D F0 F4 F6 This violation of WB ordering defeats the previous strategy for precise exception handling problem is out of order completion 1 1 2 2 3 3 4 4 stop stop fetching fetching turn turn off off writes writes let let pipeline pipeline drain drain handle handle ADD D F2 F4 F6 DIV D F0 F2 F4 ADD 3 4 5 6 7 ID M1 M2 M3 M4 IF ID EX MEM WB M5 IF ID EX MEM WB IF ID A1 IF ID 8 9 10 11 M6 M7 MEM WB A2 A3 A4 MEM WB EX MEM WB ID EX MEM WB IF ID EX MEM What happens if sub faults What about R1 CMSC 411 6 from Patterson IF And then div R1 R1 R2 SUB D F10 F12 F14 L D F2 0 R2 15 CMSC 411 6 from Patterson Possible fixes Possible fixes cont Give up and just do imprecise exception handling tempting but very annoying to users Delay WB until all previous instructions complete since so many instructions can be active this is expensive requires a lot of supporting hardware Write to memory a history file of register and memory changes so can undo instructions if necessary or keep a future file of computed results that are waiting for MEM or WB Let the exception handler finish the instructions in the pipeline and then restart the pipe at the next instruction CMSC 411 6 from Patterson CS252 S05 IF 2 17 WB 16 Have the floating point units diagnose exceptions in their first or second stages so can handle them by methods that work well for handling integer exceptions CMSC 411 6 from Patterson 18 How to detect hazards in ID A case study MIPS R4000 Early detection would prevent trouble Check for structural hazards will the divide unit clear in time will WB be possible when we need it Check for RAW data hazards will all source registers be available when needed Check for WAW data hazards Is the destination register for …