DOC PREVIEW
UMD CMSC 411 - Lecture 17 Storage Systems 1

This preview shows page 1-2 out of 6 pages.

Save
View full document
Premium Document
Do you want full access? Go Premium and unlock all 6 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Storage systems We already know about four levels of storage Registers Cache Memory Disk But we ve been a little vague on how these devices are interconnected In this unit we study Input output units such as disks and tapes Buses to connect storage devices I O performance issues Design of file systems won t talk much about this CMSC 411 Computer Systems Architecture Lecture 17 Storage Systems 1 CMSC 411 17 some from Patterson Sussman others 2 Hard Disks What it is A collection of 1 20 platters like 2 sided CD s Between 1 and 8 inches in diameter 2 5 3 5 inch most common today Rotating on a central spindle With 500 2500 tracks on each surface Divided into maybe 64 sectors Disk and Tape Technologies older disks all tracks have the same number of sectors current disks outer tracks have more sectors Larger diameter better retrieval times Smaller diameter cheaper and uses less power Disk controller provides access to 1 or more disks CMSC 411 17 some from Patterson Sussman others Disks cont Disks cont How information is retrieved by disk controller Wait for previous requests to be filled Time queuing delay A movable arm is positioned at the correct cylinder Time seek time The system waits for the correct sector to appear under the arm Time rotational latency Used for file storage slowest level of virtual memory during program execution Fig 7 1 from H P 3ed CMSC 411 17 some from Patterson Sussman others CS252 S05 4 5 CMSC 411 17 some from Patterson Sussman others 6 Disks cont Example How information is retrieved by disk controller cont Then a magnetic head senses the sector number the information recorded in the sector an error correction code and the information is transferred to a buffer Time transfer time The disk controller may impose some extra overhead Time controller time Because all of this is so expensive disk controller might also read the next sector or two hoping that the next information needed is located there prefetch or read ahead CMSC 411 17 some from Patterson Sussman others average seek time 5 ms transfer rate 10MB sec rotation speed 8000 RPM sector size 1024 bytes controller overhead 5 ms 7 Example cont Average disk access time in millisec average seek time average rotational delay transfer time controller overhead CMSC 411 17 some from Patterson Sussman others 8 Speed gap between memory and disk average seek time 5 ms average rotational delay transfer time controller overhead 5 ms Total 5 3 75 1 5 9 35 ms Fig 6 1 CMSC 411 17 some from Patterson Sussman others 9 CMSC 411 17 some from Patterson Sussman others Competitors to disks Solid state disks built from DRAMs But needs constant power Optical disks CDs DVDs Blu Ray Magnetic tapes Slower but large capacity good for backups Automated tape libraries Juke box technology Flash memory Small fast low power CMSC 411 17 some from Patterson Sussman others CS252 S05 Buses 11 10 Buses Typical bus transaction We ve seen buses before especially in the discussion of Tomasulo s algorithm CDB Main characteristic Buses are shared by several data paths and therefore can be bottlenecks CPU memory buses physically short high speed design optimized for performance I O buses long handle an unknown number of devices with unpredictable characteristics When a READ is issued Bus begins in a wait state Address sent on bus to memory with control information to signal a read When data is available the wait signal is turned off and the data is transmitted When a WRITE is issued Bus begins in a wait state Address sent on bus to memory with control information to signal a write Then the data is transmitted usually with no pause 13 CMSC 411 17 some from Patterson Sussman others Bus options Fig 7 8 H P 3ed High performance Low cost Bus width separate address and data lines multiplex address and data lines Data width wider is faster e g 64 bits narrower is cheaper e g 8 bits Transfer size multiple words have less overhead single word transfer is simpler Bus masters multiple need arbitration single no arbitration Split transactions yes separate request and reply gets higher bandwidth no continuous connection cheaper and lower latency Clocking synchronous asynchronous CS252 S05 15 The bus master does If the bus is between CPU and memory then the CPU is the bus master If it is an I O bus then there might be several devices so several bus masters and they compete for time slices on the bus In this case buses are often packet switched each device divides its message into fixed length packets and takes turns with other devices that are transmitting CMSC 411 17 some from Patterson Sussman others Synchronous vs asynchronous buses Asynchronous buses Buses that are clocked synchronous send data and addresses at fixed times so sender and receiver always know what to expect Makes them fast and cheap But restricts them to be short because of time lag problems Buses that are not clocked asynchronous use handshaking protocols to establish contact Sender puts message on bus to get the attention of receiver Receiver responds Sender transmits data Receiver sends acknowledgement of receipt Because of handshaking protocol They can be slow and expensive But it allows them to be physically long and to serve a wide variety of devices The handshaking protocols are standardized so that device manufacturers can connect to a variety of buses examples include IDE ATA SCSI USB CMSC 411 17 some from Patterson Sussman others 14 Who issues READs and WRITEs Option CMSC 411 17 some from Patterson Sussman others CMSC 411 17 some from Patterson Sussman others 17 CMSC 411 17 some from Patterson Sussman others 16 18 How is the I O bus connected How does CPU get data from I O bus Do we connect it to the memory bus or to the cache Typical solution from Fig 7 15 H P 3ed Two solutions Some mostly older machines have op codes that read or write to I O devices In memory mapped I O certain physical addresses are reserved for I O devices like disks so those reads and writes are put on the I O bus Usually I O is interrupt driven meaning that after the CPU requests a READ or WRITE it goes on with other work until the I O unit signals that it is finished CMSC 411 17 some from Patterson Sussman others 19 CMSC 411 18 some from Patterson Sussman others 20 DMA to make this work To allow the CPU to proceed need another controller to shepherd the READ or WRITE Direct memory access DMA hardware is used to record the address and the number of bytes to be transferred act as bus master initiating each


View Full Document

UMD CMSC 411 - Lecture 17 Storage Systems 1

Documents in this Course
Load more
Download Lecture 17 Storage Systems 1
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 17 Storage Systems 1 and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 17 Storage Systems 1 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?