1Textbook Chapter 5CMPE12 – Summer 2008LC-3 Instruction Set ArchitectureCMPE12 – Summer 2008 – Slides by ADB 2Instruction set architecture What is an instruction set architecture (ISA)? It is all of the programmer-visible components and operations of the computer The ISA provides all the information needed for someone to write a program in machine language  Or translate from a high-level language to machine language2CMPE12 – Summer 2008 – Slides by ADB 3Instruction set architecture Memory organization Address space (how many locations can be addressed?) Addressability (how many bits per location?) Register set How many instructions? What size? How are they used? Instruction set Opcodes Data types Addressing modesCMPE12 – Summer 2008 – Slides by ADB 4LC-3 memory Address space: 216locations  Address bus: 16 bits Addressability: 16 bits per location Data bus: 16 bits Access time: several clock cycles Volatile Loses content at power off3CMPE12 – Summer 2008 – Slides by ADB 5Registers: GPRs 8 general-purpose registers (GPUs) in the CPU’s register file Address space: 23=8 locations  Addressability: 16 bits per register Access time: 1 clock cycle Volatile Lose content at power offCMPE12 – Summer 2008 – Slides by ADB 6LC-3 special registers PC: Program Counter Contains memory address of next instruction to execute IR: Instruction Register Stores current instruction MAR: Memory Address Register Address of current memory access  MDR: Memory Data Register Data to write to or read from memory Condition codes (CC) register N, Z, P All are 16 bits except CC (3 bits)4CMPE12 – Summer 2008 – Slides by ADB 7Instructions What do instructions look like?CMPE12 – Summer 2008 – Slides by ADB 8Instruction set architecture Opcodes Data types Addressing modes5CMPE12 – Summer 2008 – Slides by ADB 9Instruction set architecture Opcodes 16 opcodes (1 unused/reserved) Operate (Logical or Arithmetic) instructions:  ADD, AND, NOT Data movement instructions:  LD, LDI, LDR ST, STR, STI LEA Control instructions:  BR, JSR/JSRR, JMP, RTI, TRAP Some opcodes set/clear condition codes, based on result: N = negative (< 0) Z = zero P = positive (> 0)CMPE12 – Summer 2008 – Slides by ADB 10Instruction set architecture Data Types 16-bit 2’s complement integer Addressing Modes  How operands are specified Or how the next instruction to execute is specified Architecture-specific An instruction can use several addressing modes6CMPE12 – Summer 2008 – Slides by ADB 11Are these enough? Are ADD, AND, and NOT enough? With only ADD, AND, and NOT: How do we subtract? How do we OR? How do we copy from one register to another? How do we initialize a register to zero?CMPE12 – Summer 2008 – Slides by ADB 12Addressing modesAn exhaustive list of the LC-3 addressing modes Immediate Register PC-Relative Base+Offset Memory-indirect7CMPE12 – Summer 2008 – Slides by ADB 13Addressing modes: Immediate Immediate: a numeric value embedded in the instruction is the actual operand.  Data movement instructions: ADD, AND, LEA Control flow instructions: none You can tell an instruction uses this addressing mode when… A constant value is explicitly specified in one of the named instructionsCMPE12 – Summer 2008 – Slides by ADB 14Instruction: ADD/ANDNote: Immediate field is sign-extended.This one means “immediate mode”Addressing mode(s):REGISTER and IMMEDIATE8CMPE12 – Summer 2008 – Slides by ADB 15Addressing modes: Register Register: a source or destination operand is specified as content of one of the registers R0-R7.  Data movement instructions: ADD, AND, NOT, LD, LDI, LDR, LEA, ST, STI, STR Control flow instructions: JMP, RET, JSRR You can tell an instruction uses this addressing mode when… A register is explicitly specified in the instructionCMPE12 – Summer 2008 – Slides by ADB 16Addressing mode(s):REGISTERInstruction: NOT Notes:  Works only with registers Src and Dstcan be the same register9CMPE12 – Summer 2008 – Slides by ADB 17Instruction: ADD/ANDThis zero means “register mode”Addressing mode(s):REGISTERCMPE12 – Summer 2008 – Slides by ADB 18Addressing modes: PC-Relative The problem: We want to specify address directly in the instruction But an address is 16 bits, and so is an instruction After subtracting 4 bits for opcode and 3 bits for register, we have only 9 bits available for address10CMPE12 – Summer 2008 – Slides by ADB 19Addressing modes: PC-Relative The solution: Use the 9 bits as a signed offset from the current PC 9 bits allows the offset range to be –256 ≤ offset ≤ +255 We can now form any address X, such that (PC – 256) ≤ X ≤ (PC +255) Remember that the PC is incremented before the instruction is executedCMPE12 – Summer 2008 – Slides by ADB 20Addressing modes: PC-Relative PC-relative: a data or instruction memory location is specified as an offset relative to the incremented PC Data movement instructions: LD, ST Control flow instructions: BR, JSR You can tell an instruction uses this addressing mode when… The instruction is one of the ones named above11CMPE12 – Summer 2008 – Slides by ADB 21Instruction: LD (Load Data)Addressing mode(s):PC-RELATIVE (and REGISTER)DR = M[PC+SX(PCoffset9)]CMPE12 – Summer 2008 – Slides by ADB 22Instruction: ST (Store Data)Addressing mode(s):PC-RELATIVE (and REGISTER)M[PC+SX(PCoffset9)] = SR12CMPE12 – Summer 2008 – Slides by ADB 23Instruction: LD/ST...LD R0, BOBLD R1, BILLADD R2, R0, R1ST R2, RESULT...BOB .FILL 0xFFFFBILL .FILL 0x0002RESULT .FILL 0x0000x3000..x3010x3011x3012x3013...x3020x3021x3022CMPE12 – Summer 2008 – Slides by ADB 24Addressing Modes: Base+Offset Problem: With PC-relative mode, we can only address data within 256 words of the instruction What about the rest of memory? How do we access it? Solution: Use a register to generate a full 16-bit address 4 bits for opcode 3 bits for source / destination register 3 bits for base register Remaining 6 bits are used as a signed offset Offset is sign-extended before adding to base register13CMPE12 – Summer 2008 – Slides by ADB 25Addressing Modes: Base+Offset Base+offset: a data