1LC-3 Instruction ProcessingTextbook chapter 4CMPE 12 – Summer 2008CMPE12 – Summer 2008 – Slides by ADB 2Phases of Instruction ProcessingDecode instructionEvaluate addressFetch operands from memoryExecute operationStore resultFetch instruction from memory2CMPE12 – Summer 2008 – Slides by ADB 3Phases of Instruction Processing Six basic phases of instruction processing F Æ D Æ EA Æ OP Æ EX Æ S Instruction fetch Instruction decode Evaluate address Fetch operands Execute Store result Notes Not all phases are needed by every instruction But all instructions will go through F and D Phases may take more than one clock cycleCMPE12 – Summer 2008 – Slides by ADB 4Phases: Fetch Load next instruction (at address stored in PC) from memory into Instruction Register (IR). Copy contents of PC into MAR. Send “read” signal to memory. Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. PC becomes PC+1.EAOPEXSFD3CMPE12 – Summer 2008 – Slides by ADB 5Phases: DecodeEAOPEXSFD First identify the opcode In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode. Depending on opcode, identify other operands from the remaining bits Example: for LDR, last six bits is offset for ADD, last three bits is second source operandCMPE12 – Summer 2008 – Slides by ADB 6Phases: Evaluate AddressEAOPEXSFD For instructions that require memory access, compute address used for access Examples: add offset to base register (as in LDR) add offset to PC add offset to zero set source registers addresses4CMPE12 – Summer 2008 – Slides by ADB 7Phases: Fetch OperandsEAOPEXSFD Obtain source operands needed to perform the operation Examples: load data from memory (LDR) read data from register file (ADD)CMPE12 – Summer 2008 – Slides by ADB 8Phases: ExecuteEAOPEXSFD Perform the operation, using the source operands Examples: send operands to ALUand assert ADD signal do nothing (e.g., for loads and stores)5CMPE12 – Summer 2008 – Slides by ADB 9Phases: Store ResultEAOPEXSFD Write results to destination(register or memory) Examples: result of ADD is placed in destination register result of memory load is placed in destination register for store instruction, data is stored to memory write address to MAR, data to MDR assert WRITE signal to memoryCMPE12 – Summer 2008 – Slides by ADB 10LC-3 Data PathFilled arrow= info to be processedUnfilled arrow= control signal6CMPE12 – Summer 2008 – Slides by ADB 11Data Path Components: Global Bus What is a bus? Global bus: Special set of wires that carry a 16-bit signal to many components Inputs to the bus are tri-state buffers that only place a signal on the bus when they are enabled Only one device speaks on the bus at any given time Control unit decides which signal drives the bus Any number of components can read the bus Control unit write-enables the destination deviceCMPE12 – Summer 2008 – Slides by ADB 12Tri-State Buffer Tri-state buffer allows some outputs to be turned off Places them in high-impedance or high-Z state Outputs can have one of three values Zero (0) One (1) Z (no output)7CMPE12 – Summer 2008 – Slides by ADB 13Global Bus What is a bus?CMPE12 – Summer 2008 – Slides by ADB 14Data Path Components: Memory Control and data registers for memory and I/O devices MAR (Memory Address Register) Holds the last address accessed MDR (Memory Data Register)  Holds the last data read Control signal for read/write8CMPE12 – Summer 2008 – Slides by ADB 15Memory, MAR, MDR Control and data registers for memory and I/O devices MAR (Memory Address Register) Holds the last address accessed MDR (Memory Data Register)  Holds the last data read Control signal for read/writeCMPE12 – Summer 2008 – Slides by ADB 16Data Path Components: ALU ALU: Arithmetic Logic Unit Inputs: one of the following Register file Immediate field Sign-extended bits from IR Output goes to bus, and then used by Condition code logic Register file  Memory9CMPE12 – Summer 2008 – Slides by ADB 17ALU Inputs: one of the following Register file Immediate field Sign-extended bits from IR Output goes to bus, and then used by Condition code logic Register file  MemoryCMPE12 – Summer 2008 – Slides by ADB 18Data Path Components: Register File Two read addresses (SR1, SR2) One write address (DR)  Inputs: one of the following Result of ALU operation  Memory read Outputs: Two 16-bit outputs used by… ALU ALU instructions Data for store instructions passes through ALU PC Branches and jumps Memory address10CMPE12 – Summer 2008 – Slides by ADB 19Register File Two read addresses (SR1, SR2) One write address (DR)  Inputs: one of the following Result of ALU operation  Memory read Outputs: Two 16-bit outputs used by… ALU ALU instructions Data for store instructions passes through ALU PC Branches and jumps Memory addressCMPE12 – Summer 2008 – Slides by ADB 20Data Path Components: PC and PCMUX PC and PCMUX Program Counter and the PC multiplexer Input to PC: one of the following (controlled by PCMUX) PC+1 from the fetch stage Output of address adder (for branches and jumps) Global bus for trap instructions11CMPE12 – Summer 2008 – Slides by ADB 21PC and PCMUX PC and PCMUX Program Counter and the PC multiplexer Input to PC: one of the following (controlled by PCMUX) PC+1 from the fetch stage Output of address adder (for branches and jumps) Global bus for trap instructionsCMPE12 – Summer 2008 – Slides by ADB 22Data Path Components: MAR and MARMUX MAR and MARMUX Inputs to MAR: one of the following (controlled by MARMUX) Output of address adder (for loads and stores) Zero-extended IR[7:0] for trap instructions12CMPE12 – Summer 2008 – Slides by ADB 23MAR and MARMUX Inputs to MAR: one of the following (controlled by MARMUX) Output of address adder (for loads and stores) Zero-extended IR[7:0] for trap instructionsCMPE12 – Summer 2008 – Slides by ADB 24Condition Codes Input  The global bus  Output N, Z, P signals Registers set only when