1LC-3 Input and OutputSummer 2008CMPE12 – Summer 2008 – Slides by ADB 2I/O: Connecting to Outside World So far, we’ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory use the TRAP calls to deal with I/O How do the TRAP calls work?2CMPE12 – Summer 2008 – Slides by ADB 3I/O devices types I/O devices are characterized by Behavior Data rate Behavior: input, output, storage Input: keyboard, motion detector, network interface Output: monitor, printer, network interface Storage: disk, CD-ROM Data rate: how fast can data be transferred? Keyboard: 100 bytes/sec Disk: 30 MB/s Network: 1 Mb/s - 1 Gb/sCMPE12 – Summer 2008 – Slides by ADB 4I/O Controller Control/Status Registers CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register Data Registers CPU transfers data to/from device Device electronics Performs actual operation pixels to screen, bits to/from disk, characters from keyboardGraphics ControllerControl/StatusOutput DataElectronicsCPUdisplay3CMPE12 – Summer 2008 – Slides by ADB 5Programming Interface How are device registers identified? Memory-mapped vs. I/O-mapped (special instructions) How is timing of transfer managed? Asynchronous vs. synchronous Who controls transfer? CPU (polling) vs. device (interrupts)CMPE12 – Summer 2008 – Slides by ADB 6I/O-mapped I/O Specific opcode(s) for I/O (e.g. IN and OUT in x86) Two separate addressing spaces4CMPE12 – Summer 2008 – Slides by ADB 7Memory-Mapped I/O Assign a memory address to each device register Use same memory data movement instructions (load/store) for control and data transfer The hardware will figure out that the instruction refers to a device and not to the memoryCMPE12 – Summer 2008 – Slides by ADB 8Transfer Timing I/O events generally happen much slowerthan CPU cycles Synchronous Data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous Data rate less predictable CPU must synchronize with device,so that it doesn’t miss data or write too quickly5CMPE12 – Summer 2008 – Slides by ADB 9Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data “Are we there yet? Are we there yet?” Interrupts Device sends a special signal to CPU whennew data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. “Wake me up when we get there.”CMPE12 – Summer 2008 – Slides by ADB 10LC-3: Memory-mapped IO (Table A.3 in text)Bit [15] is one when device ready to display another char on screen.Display Status Register (DSR)xFE04Character written to bits [7:0] will be displayed on screen.Display Data Register (DDR)xFE06Bits [7:0] contain the last character typed on keyboard.Keyboard Data Reg (KBDR)xFE02Bit [15] is one when keyboard has received a new character.Keyboard Status Reg (KBSR)xFE00FunctionI/O RegisterLocation6CMPE12 – Summer 2008 – Slides by ADB 11Input from the keyboard When a character is typed: Its ASCII code is placed in bits [7:0] of KBDR(bits [15:8] are always zero) The “ready bit” (KBSR[15]) is set to one Keyboard is disabled -- any typed characters will be ignored When KBDR is read: KBSR[15] is set to zero, that is Keyboard is enabledKBSRKBDR15 8 7 01514 0keyboard dataready bitCMPE12 – Summer 2008 – Slides by ADB 12Basic polling routine: GETCnewchar?readcharacterYESNOPollingPOLL LDI R0, KBSRPtrBRzp POLLLDI R0, KBDRPtr...KBSRPtr .FILL xFE00KBDRPtr .FILL xFE02(look it up – it’s GETC, at x0400)7CMPE12 – Summer 2008 – Slides by ADB 13Hardware implementation of memory-mapped inputAddress Control Logicdetermines whether MDR is loaded from Memory or from KBSR/KBDR.CMPE12 – Summer 2008 – Slides by ADB 14Output to Monitor When Monitor is ready to display another character: The “ready bit” (DSR[15]) is set to one When data is written to Display Data Register: DSR[15] is set to zero Character in DDR[7:0] is displayed  Any other character data written to DDR is ignored while DSR[15] is zeroDSRDDR15 8 7 01514 0output dataready bit8CMPE12 – Summer 2008 – Slides by ADB 15Basic polling routine: PUTCscreenready?writecharacterYESNOPollingPOLL LDI R1, DSRPtrBRzp POLLSTI R0, DDRPtr...DSRPtr .FILL xFE04DDRPtr .FILL xFE06CMPE12 – Summer 2008 – Slides by ADB 16Hardware implementation of memory-mapped outputSets LD.DDRor selects DSR as input.9CMPE12 – Summer 2008 – Slides by ADB 17Keyboard Echo Routine Usually, input character is also printed to screen.newchar?readcharacterYESNOscreenready?writecharacterYESNOPOLL1 LDI R0, KBSRPtrBRzp POLL1LDI R0, KBDRPtrPOLL2 LDI R1, DSRPtrBRzp POLL2STI R0, DDRPtr...KBSRPtr .FILL xFE00KBDRPtr .FILL xFE02DSRPtr .FILL xFE04DDRPtr .FILL xFE06CMPE12 – Summer 2008 – Slides by ADB 18Interrupt-Driven I/O Polling consumes a lot of cycles, especially for rare events – these cycles can be used for computation. Example: Process previous input while collectingcurrent input. In a more efficient approach, an external device can:(1) Force currently executing program to stop;(2) Have the processor satisfy the device’s needs; and(3) Resume the stopped program as if nothing happened.10CMPE12 – Summer 2008 – Slides by ADB 19Interrupt-Driven I/O To implement an interrupt mechanism, we need three things A way for the I/O device to signal the CPU that an interesting event has occurred A way for the CPU to test whether the interrupt signal is set  A way for the CPU to test whether its priority is higher than the current program’sCMPE12 – Summer 2008 – Slides by ADB 20Interrupt generation Software sets "interrupt enable" (IE) bit in device register (interrupt mask) When ready bit is set and IE bit is set, interrupt is signaled.KBSR1514 0ready bit13interrupt enable bitinterrupt signal to processor11CMPE12 – Summer 2008 – Slides by ADB 21Testing for the interrupt signal CPU looks at signal between STORE and FETCH phases If not set, continue with next instruction If set, transfer control to interrupt service routineEAEAOPOPEXEXSSFFDDinterruptsignal?Transfer toISRTransfer toISRNOYESCMPE12 – Summer 2008 –