CMPE12 Cyrus Bazeghi1LC-3Instruction Set Architecture (Ch5)CMPE12 Cyrus Bazeghi2Instruction Set ArchitectureISA is all of the programmer-visiblecomponents and operations of the computer.– memory organization• address space -- how may locations can be addressed?• addressibility -- how many bits per location?– register set• how many? what size? how are they used?– instruction set• opcodes• data types• addressing modesThe ISA provides all the information needed for someone to write a program in machine language (or translate from a high-level language to machine language).CMPE12 Cyrus Bazeghi3Memory vs. RegistersMemory– address space: 216locations (16-bit addresses)– addressability: 16 bitsRegisters– temporary storage, accessed in a single machine cycle• accessing memory generally takes longer than a single cycle– eight general-purpose registers: R0 - R7• each is 16 bits wide• how many bits to uniquely identify a register?– other registers• not directly addressable, but used/effected by instructions• PC (program counter), condition codesLC-3 OverviewCMPE12 Cyrus Bazeghi4Instruction SetOpcodes– 15 opcodes–Operate(Logical or Arithmetic) instructions: ADD, AND, NOT–Data movementinstructions: LD, LDI, LDR, LEA, ST, STR, STI–Controlinstructions: BR, JSR/JSRR, JMP, RTI, TRAP– some opcodes set/clear condition codes, based on result:• N = negative (< 0), Z = zero, P = positive (> 0)Data Types– 16-bit 2’s complement integer (we’ll get to that soon)Addressing Modes– How is the location of an operand specified?– non-memory addresses: immediate, register– memory addresses: PC-relative, indirect, base+offsetLC-3 OverviewCMPE12 Cyrus Bazeghi5Operate InstructionsOnly three operations: ADD, AND, NOTSource and destination operands are registers– These instructions do notreference memory.– ADD and AND can use “immediate” mode,where one operand is hard-wired into the instruction.Will show dataflow diagram with each instruction.– illustrates whenand wheredata moves to accomplish the desired operationLC-3 OverviewCMPE12 Cyrus Bazeghi6NOTNote: Src and Dstcould be the sameregister.Note: works only with registers.InstructionsCMPE12 Cyrus Bazeghi7ADD/ANDThis zero means “register mode”InstructionsCMPE12 Cyrus Bazeghi8ADD/ANDNote: Immediate field is sign-extended.This one means “immediate mode”InstructionsCMPE12 Cyrus Bazeghi9Using Operate InstructionsWith only ADD, AND, NOT…– How do we subtract?– How do we OR?– How do we copy from one register to another?– How do we initialize a register to zero?CMPE12 Cyrus Bazeghi10Data Movement InstructionsLoad -- read data from memory to register– LD: PC-relative mode– LDR: base+offset mode– LDI: indirect modeStore -- write data from register to memory– ST: PC-relative mode– STR: base+offset mode– STI: indirect modeLoad effective address -- compute address, save in register– LEA: immediate mode–does not access memoryCMPE12 Cyrus Bazeghi11Addressing Modes• How memory is addressed.• Different instructions use different addressing modes.• Some instructions support more than one addressing mode.CMPE12 Cyrus Bazeghi12LC-3 Addressing Modes• PC-Relative– Address is a displacement from PC • Indirect– Use PC-Relative to get address from memory• Base plus Offset– Use contents of a register as base address and add offset to find address (most common for load/store architectures)CMPE12 Cyrus Bazeghi13PC-RelativeThe Problem:We want to specify address directly in the instruction– But an address is 16 bits, and so is an instruction!– After subtracting 4 bits for opcode and 3 bits for register, we have only 9 bits available for address.Addressing ModesCMPE12 Cyrus Bazeghi14PC-Relative Addressing ModeThe Solution:Use the 9 bits as a signed offsetfrom the current PC.9 bits allows the offset range to be:-256 ≤ offset ≤ +255We can now form any address X, such that:(PC – 256) ≤ X ≤ (PC +255)Remember that the PC is incremented as part of the FETCH phase; This is done before the EVALUATE ADDRESS stage.CMPE12 Cyrus Bazeghi15LD (Load Data)PC-Relative Addressing ModeCMPE12 Cyrus Bazeghi16ST (Store Data)PC-Relative Addressing ModeCMPE12 Cyrus Bazeghi17IndirectThe Problem:With PC-relative mode, we can only address data within 256 words of the instruction.– What about the rest of memory? How do we access it?Addressing ModesCMPE12 Cyrus Bazeghi18Solution #1:– Read address from memory location, then load/store to that address.First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store.Indirect Addressing ModeCMPE12 Cyrus Bazeghi19LDIIndirect Addressing ModeCMPE12 Cyrus Bazeghi20STIIndirect Addressing ModeCMPE12 Cyrus Bazeghi21Base + OffsetRemember The Problem:With PC-relative mode, can only address data within 256 words of the instruction.– What about the rest of memory? How do we access it?Addressing ModesCMPE12 Cyrus Bazeghi22Solution #2:– Use a register to generate a full 16-bit address.4 bits for opcode, 3 bits for src/dest register, 3 bits for baseregister – the remaining 6 bits are used as a signed offset.– Offset is sign-extendedbefore adding to base register.Base + Offset Addressing ModeCMPE12 Cyrus Bazeghi23LDRBase + Offset Addressing ModeCMPE12 Cyrus Bazeghi24STRBase + Offset Addressing ModeCMPE12 Cyrus Bazeghi25Load Effective AddressComputes address like PC-relative (PC plus signed offset) and stores the result into a register.Note: The addressis stored in the register, not the contents of the memory location.InstructionsCMPE12 Cyrus Bazeghi26LEA (Immediate)InstructionsCMPE12 Cyrus Bazeghi27Example CodeAddress Instruction Bits Commentsx30F61 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1LEAR1  PC – 3 = x30F4x30F70 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0ADDR2  R1 + 14 = x3102x30F80 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1STM[PC - 5]  R2M[x30F4]  x3102x30F90 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0ANDR2  0x30FA0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1ADDR2  R2 + 5 = 5x30FB0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0STRM[R1+14]  R2M[x3102]  5x30FC1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1LDIR3  M[M[x30F4]]R3  M[x3102]R3  5opcodeInstructionCMPE12 Cyrus Bazeghi28Control InstructionsUsed to alter the sequence of instructions. This is done by changing the PC.Conditional Branch– branch is takenif a specified condition is true• signed offset is added to PC to yield new PC– else, the branch is not taken• PC