LC-3 ArchitectureCISC vs. RISCWhat is “Modern”Slide 4Instruction Fetch / Execute CycleSlide 6Slide 7Slide 8Slide 9Slide 10Breaking down an instructionThe Stored Program ComputerFirst Draft of a Report on EDVACVon Neumann Model*Locality of referenceMemoryInterface to MemoryProcessing UnitInput and OutputControl UnitInstructionsSlide 22Ex: LC-3 ADD InstructionEx: LC-3 LDR InstructionInstruction ProcessingFETCHDECODEEVALUATE ADDRESSFETCH OPERANDSEXECUTESTORE RESULTChanging the Sequence of InstructionsSlide 33Ex: LC-3 JMPInstruction Processing SummarySlide 36Questions?Slide 381LC-3 ArchitectureLC-3 ArchitecturePatt and Patel Ch. 4Patt and Patel Ch. 42CISC vs. RISCCISC vs. RISC•CISC : Complex Instruction Set ComputerCISC : Complex Instruction Set ComputerLots of instructions of variable size, very Lots of instructions of variable size, very memory optimal, typically less registers.memory optimal, typically less registers.•RISC : Reduced Instruction Set Computer RISC : Reduced Instruction Set Computer Less instructions, all of a fixed size, more Less instructions, all of a fixed size, more registers, optimized for speed. Usually registers, optimized for speed. Usually called a “Load/Store” architecture.called a “Load/Store” architecture.3What is “Modern”What is “Modern”•For embedded applications and for For embedded applications and for workstations there exist a wide workstations there exist a wide variety of CISC and RISC and CISCy variety of CISC and RISC and CISCy RISC and RISCy CISC.RISC and RISCy CISC.•Most current PCs use the best of Most current PCs use the best of both worlds to achieve optimal both worlds to achieve optimal performance.performance.4LC-3 ArchitectureLC-3 Architecture•Very RISC, only 15 instructionsVery RISC, only 15 instructions•16-bit data and address16-bit data and address•8 general purpose registers (GPR)8 general purpose registers (GPR)•Program Counter (PC)Program Counter (PC)•Instruction Register (IR)Instruction Register (IR)•Condition Code Register (CC)Condition Code Register (CC)•Process Status Register (PSR)Process Status Register (PSR)5Instruction Fetch / Execute Instruction Fetch / Execute CycleCycleIn addition to input & output a program In addition to input & output a program also: also: •Evaluates arithmetic & logical functions to Evaluates arithmetic & logical functions to determine values to assign to variable.determine values to assign to variable.•Determines the order of execution of the Determines the order of execution of the statements in the program.statements in the program.•In assembly this distinction is captured in the In assembly this distinction is captured in the notion of notion of arithmeticarithmetic, , logicallogical, and , and controlcontrol instructions.instructions.6Arithmetic and logical instructions evaluate variables and assign new values to variables.Control instructions test or compare values of a variable and makes decisions about what instruction is to be executed next.Program Counter (PC)Basically the address at which the current executing instruction exists.Instruction Fetch / Execute Cycle71. load rega, 102. load regb, 203. add regc, rega, regb4. beq regc, regd, 85. store regd, rege6. store regc, regd7. load regb, 158. load rega, 30PCAddress*Note: This is just pseudo assembly codeInstruction Fetch / Execute Cycle8The CPU begins the execution of an instruction by supplying the value of the PC to the memory & initiating a read operation (fetch).The CPU “decodes” the instruction by identifying the opcode and the operands.PC increments automatically unless a control instruction is used.Instruction Fetch / Execute Cycle9Instruction Fetch / Execute CycleFor example:For example:PC PC  ADD A, B, C ADD A, B, C•CPU fetches instructionCPU fetches instruction•Decodes it and sees it is an add operation, Decodes it and sees it is an add operation, needs to get values for the variables “B” & “C”needs to get values for the variables “B” & “C”•Gets the variable “B” from a register or memoryGets the variable “B” from a register or memory•Does the same for variable “C”Does the same for variable “C”•Does the “add” operation and stores the result Does the “add” operation and stores the result in location register for variable “A”in location register for variable “A”10Branch – like a goto instruction, next instruction to be fetched & executed is an instruction other than the next in memory.ADD A, B, CBRn fredADD A, D, 3fred ADD A, D, 4If A is negative then next instruction to be executed is at fred, which is just an address*Note: This is almost real LC-3 assemblyInstruction Fetch / Execute Cycle11Breaking down an Breaking down an instructioninstructionADD a, b, cADD a, b, ca b caddOpcodeDestination registerSource registers/immediate12The Stored Program ComputerThe Stored Program Computer1943: ENIAC1943: ENIAC–Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?)–Hard-wired program -- settings of dials and switches.1944: Beginnings of EDVAC1944: Beginnings of EDVAC–among other improvements, includes program stored in memory1945: John von Neumann1945: John von Neumann–wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC13First Draft of a Report on First Draft of a Report on EDVAC EDVAC •The basic structure proposed in the draft The basic structure proposed in the draft became known as the “von Neumann became known as the “von Neumann machine” (or model). machine” (or model). •This machine/model had five main This machine/model had five main components:components:–a memory, containing instructions and data–a processing unit, for performing arithmetic and logical operations–a control unit, for interpreting instructions–and input and output to get data into and out of the system.14Von Neumann Model*Von Neumann Model*M E M O R YC O N T R O L U N I TM A R M D RI RP R O C E S S I N G U N I TA L UT E M PP CO U T P U TM o n i t o rP r i n t e rL E DD i s kI N P U TK e y b o a r dM o u s eS c a n n e rD i s k* A slightly modified version of Von Neumann’s original diagram15Locality of referenceLocality of reference•We need techniques to reduce the instruction size. We need techniques to reduce the instruction size. From observation of programs we see that a small From observation of