1LC-3 Instruction ProcessingTextbook chapter 4CMPE 12 – Summer 2008CMPE12 – Summer 2008 – Slides by ADB 2Phases of Instruction ProcessingDecode instructionDecode instructionEvaluate addressEvaluate addressFetch operands from memoryFetch operands from memoryExecute operationExecute operationStore resultStore resultFetch instruction from memoryFetch instruction from memory2CMPE12 – Summer 2008 – Slides by ADB 3Phases of Instruction Processing Six basic phases of instruction processing F Æ D Æ EA Æ OP Æ EX Æ S Instruction fetch Instruction decode Evaluate address Fetch operands Execute Store result Notes Not all phases are needed by every instruction But all instructions will go through F and D Phases may take more than one clock cycleCMPE12 – Summer 2008 – Slides by ADB 4Phases: Fetch Load next instruction (at address stored in PC) from memory into Instruction Register (IR). Copy contents of PC into MAR. Send “read” signal to memory. Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. PC becomes PC+1.EAEAOPOPEXEXSSFFDD3CMPE12 – Summer 2008 – Slides by ADB 5Phases: DecodeEAEAOPOPEXEXSSFFDD First identify the opcode In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode. Depending on opcode, identify other operands from the remaining bits Example: for LDR, last six bits is offset for ADD, last three bits is second source operandCMPE12 – Summer 2008 – Slides by ADB 6Phases: Evaluate AddressEAEAOPOPEXEXSSFFDD For instructions that require memory access, compute address used for access Examples: add offset to base register (as in LDR) add offset to PC add offset to zero4CMPE12 – Summer 2008 – Slides by ADB 7Phases: Fetch OperandsEAEAOPOPEXEXSSFFDD Obtain source operands needed to perform the operation Examples: load data from memory (LDR) read data from register file (ADD)CMPE12 – Summer 2008 – Slides by ADB 8Phases: ExecuteEAEAOPOPEXEXSSFFDD Perform the operation, using the source operands Examples: send operands to ALUand assert ADD signal5CMPE12 – Summer 2008 – Slides by ADB 9Phases: Store ResultEAEAOPOPEXEXSSFFDD Write results to destination(register or memory) Examples: result of ADD is placed in destination register result of memory load is placed in destination register for store instruction, data is stored to memory write address to MAR, data to MDR assert WRITE signal to memoryCMPE12 – Summer 2008 – Slides by ADB 10LC-3 Data PathFilled arrow= info to be processedUnfilled arrow= control signal6CMPE12 – Summer 2008 – Slides by ADB 11Data Path Components: Global Bus What is a bus? Global bus: Special set of wires that carry a 16-bit signal to many components Inputs to the bus are tri-state buffers that only place a signal on the bus when they are enabled Only one device speaks on the bus at any given time Control unit decides which signal drives the bus Any number of components can read the bus Control unit write-enables the destination deviceCMPE12 – Summer 2008 – Slides by ADB 12Tri-State Buffer Tri-state buffer allows some outputs to be turned off Places them in high-impedance or high-Z state Outputs can have one of three values Zero (0) One (1) Z (no output)7CMPE12 – Summer 2008 – Slides by ADB 13Global Bus What is a bus?CMPE12 – Summer 2008 – Slides by ADB 15Memory, MAR, MDR Control and data registers for memory and I/O devices MAR (Memory Address Register) Holds the last address accessed MDR (Memory Data Register) Holds the last data read Control signal for read/write8CMPE12 – Summer 2008 – Slides by ADB 17ALU Inputs: one of the following Register file Immediate field Sign-extended bits from IR Output goes to bus, and then used by Condition code logic Register file MemoryCMPE12 – Summer 2008 – Slides by ADB 19Register File Two read addresses (SR1, SR2) One write address (DR) Inputs: one of the following Result of ALUoperation Memory read Outputs: Two 16-bit outputs used by… ALU ALU instructions Data for store instructions passes through ALU9CMPE12 – Summer 2008 – Slides by ADB 21PC and PCMUX PC and PCMUX Program Counter and the PC multiplexer Input to PC: one of the following (controlled by PCMUX) PC+1 from the fetch stage Output of address adder (for branches and jumps) Global bus for trap instructionsCMPE12 – Summer 2008 – Slides by ADB 23MAR and MARMUX Inputs to MAR: one of the following (controlled by MARMUX) Output of address adder (for loads and stores) Zero-extended IR[7:0] for trap instructions10CMPE12 – Summer 2008 – Slides by ADB 24Condition Codes Input The global bus Output N, Z, P signals Registers set only when control unit enables them (LD.CC) Certain instructions set the codes ADD, AND, NOT, LD, LDI, LDR, LEACMPE12 – Summer 2008 – Slides by ADB 25Data Path Components: Finite State Machine On each machine cycle, FSM changes control signals for next phase of instruction processing Who drives the bus? GatePC, GateALU, … Which registers are write-enabled? LD.IR, LD.REG, … Which operation should the ALU perorm? ALUK … Logic includes opcode decoder, etc.11CMPE12 – Summer 2008 – Slides by ADB 26FiniteState Machine On each machine cycle, FSMchanges control signals for next phase of instruction processing Who drives the bus? GatePC, GateALU, … Which registers are write-enabled? LD.IR, LD.REG, … Which operation should the ALU perorm? ALUK … Logic includes opcodedecoder, etc.CMPE12 – Summer 2008 – Slides by ADB 27Tracing the Data Path Through the LC-3 Example 1 ADD R2, R0, R1 Example 2 STR R3, R5, xB Example 3 BRz ENDLOOP12CMPE12 – Summer 2008 – Slides by ADB 28Example 1: 1a. Fetch (step 1)x30A2 add R2,R0,R1System bus:CMPE12 – Summer 2008 – Slides by ADB 29Example 1: 1b. Fetch (step 2)x30A2 add R2,R0,R1System bus:13CMPE12 – Summer 2008 – Slides by ADB 30Example 1: 2. Instruction Decodex30A2 add R2,R0,R1System bus:CMPE12 – Summer 2008 – Slides by ADB 31Example 1: 3. Evaluate Addressx30A2 add R2,R0,R1System bus:14CMPE12 – Summer 2008 – Slides by ADB
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