7 THE SUBMICRON MOSFET We now consider what happens when a MOSFET is scaled i e reduced in size to the point where the long channel equations fail to predict some important effects We look first at the general issue of scaling and continue with some effects observed in small devices We should keep in mind that accurate modeling requires 2D simulation We can extract some important physics using intuition and 1D modeling however and we will do that where we can We will also look at reducing the 2D Poisson Equation to 1D by making some approximations 7 1 SCALING RULES There have been proposed several sets of rules for scaling for the purpose of discovering as much as possible the electrical consequences of MOSFET size reduction Principle among these are rules by Dennard in 1974 1 m channel length and Baccarani in 1984 0 25 m By scaling we hope to Increase packing density and chip functionality Increase device current and speed Lower cost increase cost effectiveness but the trade offs are Mobility degradation due to increased vertical fields Velocity saturation due to increased lateral fields Charge sharing by drain short channel effects DIBL Increased drain source resistance due to reduced area for current flow Hot carrier effects 7 1 1 Full Scaling Reference Robert H Dennard Fritz H Gaensslen Hwa Nien Yu V Leo Rideout Ernest Bassours and Andre R LeBlanc Design of Ion Implanted MOSFETs with Very Small Physical Dimensions IEEE J Solid State Circuits SC 9 5 256 1974 Dennard et al considered full scaling by a factor 1 Device size is reduced as follows linear dimensions x d ox x j x voltage doping N B N B 1 MOSFET parameters are changed as follows current I D eff W ox L d ox VG VT 1VD V D ID power P I V 2 P 2 power delay product P t Pt 3 7 1 2 Generalized Scaling Reference Giorgio Baccarani Matthew R Wordeman and Robert H Dennard Generalized Scaling Theory and Its Application to a 0 25 m MOSFET Design IEEE Transactions on Electron Devices ED 31 4 452 1984 Baccarani recognized that full scaling is not sufficiently flexible for sub m devices because Variation in kT q at elevated T gives unacceptable VT and VT is too low Junction built in potentials cannot be scaled Solution Allow for different length and voltage scales Also arrange for constant electric field voltage linear dimension x Doping and carrier concentrations x n p N B N 2 This leaves Poisson s equation invariant i e electric fields are preserved for 1 D 2 2 q 2 q 2 2 Si Si x x 2 In practice voltages are scaled less aggressively than linear dimensions because of the limitation on variations in kT q and for circuit considerations including adequate noise margins This means that electric fields tend to increase rather than remain constant 7 1 3 Empirical Relation for Long Channel Behavior Because of limitations mentioned above it should be noted that neither the scaling rules presented by Dennard nor those by Baccarani have been implemented J R Brews notes a purely empirical relation describing the minimum channel length for long channel behavior Reference J R Brews et al Generalized Guide to MOSFET Miniaturization IEEE Electron Device Letters EDL 1 2 1980 In this scaling scheme the goal is to have the scaled device behave like a long channel device Criteria are as follows Dependence of drain current on channel length is 1 L within 10 Subthreshold current does not depend on VDS see DIBL below where VDS influences subthreshold current in short channel devices With these constraints Brews et al show that the minimum channel length for long channel behavior is related to other parameters as Lmin A r j t ox wS wD 2 1 3 As long as the channel length exceeds Lmin any combination of the other parameters is acceptable In this equation the junction depth rj and the S D depletion widths w are in microns and the oxide thickness tox is in The parameter A is a fitting parameter and A 0 41 1 3 Note that this equation is empirical Wolf Fig 5 44 7 1 4 Off Current Scaling A more complex method of controlling off state current involves specifying a channel doping profile which gives an acceptably small off state current and threshold voltage in a device with as small a channel length as possible Reference J R Brews K K Ng and R K Watts The Submicron Silicon MOSFET Ch 1 2327 Submicron Integrated Circuits Ed R K Watts Wiley Interscience 1989 3 In this approach the off state current is related to the carrier density in the MOSFET channel Knowing carrier densities allows selection of an appropriate VT and channel threshold adjust profile 7 2 SMALL MOSFET MODELING 7 2 5 Charge Sharing Models It is observed that the threshold voltage of small devices L 1 m is different than is predicted by the long channel theories and that VT is a function of channel length Several factors contribute to the change in VT some causing it to increase others to decrease The observed threshold voltage will therefore depend on which of these factors dominates the device behavior Some simple ideas to explain these phenomena are discussed next These models are known as Charge Sharing Models to indicate that depletion region charge is not controlled entirely by the gate but that the source and drain regions also control some of this charge 7 2 5 1 Short Channel Effect In small MOSFETs the presence of p n junction depletion regions in the vicinity of the channel modify the ID VGS relationship causing VT to decrease with decreasing channel length Model Intrusion of S D depletion regions into the channel causes the gate to have control over less bulk charge than in long channel devices Thus VT is lowered Analysis for VD VS 0 Uyemura Figure 2 4 To account for reduced charge control we modify the bulk charge term in VT by the factor QB Q L L QB B f C ox C ox L C ox 1 L L L1 average channel length and the form factor f 1 The form 2 L factor can be treated as a fitting parameter or approximated as follows where L Assume S D diffusions are circular w radius xj S D depletion regions are same depth as channel depletion region w Call this distance xdm 4 xdm 2 Si 2 qN B F Since Vbi 2 F this is reasonable Now see Uyemura Fig 2 4 x j xdm 2 x 2 dm x j L 2 This gives L x j x 2j 2 x j x dm Thus the form factor is f 1 xj L 1 2 x dm 1 xj and the threshold voltage becomes VTSCE V FB 2 F x qDI 1 2 Si qN B 2 F 1 C ox C ox L j 1 2 x dm 1 xj We define VT from VT short VT long VT which gives VT 1 C ox 2q Si N …