8 ULTRA SMALL MOS PERFORMANCE FABRICATION AND MATERIALS ISSUES In this section we review some MOSFET physics materials and device technologies with a view toward ultra small devices We will look at materials technologies including ultra thin oxides and alternative dielectrics device technologies including CMOS and SOI and memory cells including SRAM DRAM and non volatile memory such as FLASH 8 1 GENERAL CONSIDERATIONS References Yuan Taur D A Buchanan Wei Chen D J Frank K E Ismail S H Lo G A SaiHalasz R G Viswanathan H J C Wann S J Wind and Hon Sum Wong CMOS Scaling into the Nanometer Regime Proc IEEE 85 4 486 1997 D A Buchanan Scaling the Gate Dielectric Materials Integration and Reliability IBM J Research and Development 43 3 pp 245 264 1999 C H Wann Kenji Noda T Tanaka M Yoshida and C Hu A Comparative Study of Advanced MOSFET Concepts IEEE Trans Electron Devices 43 10 1742 1996 C Fiegna H Iwai T Wada M Saito E Sangiorgi and B Ricco Scaling the MOS Transistor Below 0 1 mm Methodology Device Structures and Technology Requirements IEEE Trans Electron Devices 41 6 941 1994 S Asai and Y Wada Technology Challenges for Integration Near and Below 0 1 m Proc IEEE 85 4 505 1997 D Goldhaber Gordon M S Montemerlo J Christopher Love G J Optick and J C Ellenbogen Overview of Nanoelectronic Devices Proc IEEE 85 4 521 1997 We begin with a review by Taur et al who have identified several areas considered to present challenges in the sub 0 1 m regime Taur et al Figure 1 8 1 1 Gate Oxide Thickness Taur et al Fig 13 Note the enormous increase in gate current as the oxide is scaled below 20 corresponding to a channel length of 25 50 nm for high performance logic devices DRAM can tolerate less leakage and therefore requires larger oxide thicknesses 8 1 8 1 2 Other Issues Poly Depletion Creation of a depletion region in the poly gate introduces a series capacitance again lowering effective gate capacitance See Section 8 5 5 below Taur et al Figure 14 Quantum Mechanical Threshold Shift Since QI is distributed away from the interface in discrete energy levels there is a shift in the threshold voltage to larger values with the effect increasing for larger vertical fields Random Dopant Distribution For small devices there is a noticeable shift in VT due to random fluctuations in the number and distribution of dopants in the channel The figure in Taur is for L 0 1 m W 0 5 m tox 30 and NB averaging 8 6 x 1017 cm 3 Under these conditions the number of dopant atoms in the channel is on the order of hundreds Taur Figure 18 8 2 ULTRA SMALL DEVICES As of 2004 the smallest reported operating MOSFET had a channel length of 6 nm 0 006 m A look at this and other efforts at ultra small devices follows 8 2 1 Sai Halasz et al Low T 0 1 m MOSFET Reference G A Sai Halasz et al Design and Experimental Technology for 0 1 m GateLength Low T Operation FETs IEEE Electron Device Lett EDL 8 10 463 1987 Sai Halasz Fig 3 4 5 Operation of this device was designed for LN2 temperature for the following reasons Subthreshold conduction reduced Change in VT with change in T reduced Lower line resistance Better punch through resistance Idea Velocity saturation in small devices no increase in performance with increase in power dissipation Therefore we need to reduce voltage levels which means low T operation Lithography Direct write e beam Performance 8 2 77 K 0 1 m device gm 760 mS mm 300 K device functions but less well than at 77 K Smallest Device L 0 07 m 700 8 2 2 Iwai et al 0 04 m MOSFET 1 5 nm gate oxide Reference H Iwai et al Toshiba Japan The Future of Ultra Small Geometry MOSFETs Beyond 0 1 Micron Microelectronic Engineering 28 1995 p 147 154 Scaling to sub 0 1 m Principle concerns Punch through short channel effects Hot carrier susceptibility Increased series resistance due to reduced size of S D diffusions 8 2 2 1 Fabrication Approach I Iwai Figs 5 8 6 7 Reduce L to 40 nm 400 dox to 3 0 nm junction depths xj 10 nm Oxygen plasma ashing to define gate PSG solid diffusion for S D junctions Operation see Iwai Figs 8a f Very little SCE observed in 8a 8c except for some evidence of DIBL at large VD Performance increase of 30 is observed for ID as seen in Fig 8d This is not a large increase and is limited by increased S D resistance and velocity saturation Supply Voltage 1 5V suppresses hot carrier effects as seen in 8e and 8f Subthreshold current Isub is an indicator of hot carrier injection as will be discussed in the next chapter No velocity overshoot is observed from transconductance measurements 8 2 2 2 Fabrication Approach II Increase ID by reducing dox to 1 5 nm increase L to 140 90 nm xj 30 nm Performance Gate leakage as a fraction of channel current drops with L I gate drain L channel L2channel I channel 1 Lchannel 8 3 Record high 1400 mA m ID and 1010 mS m at 1 5 V Iwai Fig 11 8 2 3 Sub 30 nm NMOS Devices Reference G Bertrand et al Towards the Limits of Conventional MOSFETs Case of Sub30 nm NMOS Devices Solid State Electronics 48 2004 505 Fabrication 1 2 nm SiO2 gate oxide n polysilicon gates B implant for threshold adjust BF2 implant for halo and super halo no channel implant Lithography e beam deep UV hybrid Issues SCE Effects SCE punch through is observed despite several different halo designs Rsd Halos tend to compensate S D which leads to higher Rsd Taur shift and ratio method used but found to be inaccurate at these dimensions Halo benefit disappears below 50 nm more clever doping schemes or less rapidlydiffusing dopants e g In will be needed Issues Performance Current still improves with decreasing Lg Transconductance is poor for small Lg unless Rsd can be controlled No velocity overshoot is observed Bertrand Figs 1 2 4 6 8 2 4 IBM Hopewell Junction 6 nm 0 006 m MOSFET Reference B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 Fabrication SOI Silicon on Insulator thin c Si layer on 1500 buried SiO2 EOT 1 2 or 2 2 nm nitrided SiO2 gate oxide n polysilicon gates 8 4 No channel doping halo doping servers to reduce SCE and raise VT Raised S D 4 8 nm selective Si epitaxy Issues SCE Effects SCE seems to be fairly well controlled especially with strong halo implants and thin oxides Issues Performance IDS at 6 nm is low possibly because of process induced variations coupled with the ultra thin Si layer in the channel and the S D extension regions 8 2 5 Just How Low Can We Go Reference H …