Advanced MOS Devices Chapter 5 Charge Coupled Devices Cullen College of Engineering Department of Electrical and Computer Engineering Dr Len Trombetta Spring 2011 Bucket Brigade Device We inject charge by forward biasing a diode this is the signal Idea By alternating the relative size of 1 2 charge can be moved to the right This device can be used to delay a signal which is useful for filtering applications We need some sort of readout circuitry that will detect the charge when it gets to the end of the line Charge Coupled Device CCD Surface Channel CCD We replace the source drain idea with charge packets formed under an MOSC gate Here the charge moves along the surface of the device actually the Si SiO2 interface This is a three phase CCD three different potentials confine and move the charge In this figure the relative size of the potentials at adjacent gates is such that the charge is confined to the central gate Bulk Channel CCD Here the charge moves below the surface which keeps it away from interface states that would impede the flow or even capture charge thus removing it from the signal Deep Depletion Increasing time The points A B C on the CV curve refer to the figures to the left Relation between gate voltage surface potential s and inversion charge QI Section 3 4 2 2 VG S QI Cox qN B w Cox Note that VG is fixed but QI is increasing with time and hence s and w change Fig 3 8 We need only the surface potential to indicate the extent to which the inversion layer has formed The analogy with water in a well is clear In this figure charge is intended to be confined under the gate labeled by 2 At a given gate voltage VG if QI becomes too large the surface potential will not be able to confine the charge If the voltages on adjacent gates are VH and VL the maximum charge we can store is Qmax Cox VH VL Charge is confined in the lateral direction by increasing the oxide thickness on either side of where the charge packet is to be stored Higher doping density moves the threshold voltage to larger values Thicker oxide moves the threshold voltage to larger values Robert F Pierret Semiconductor Device Fundamentals Addison Wesley 1996 Electrical Signal Input Input gate A differential voltage is applied to gates VG1 VG2 The depth under this gate is then proportional to the signal When the diode is forward biased charge fills in proportion to the signal Bulk Channel CCD The disadvantage to this structure is that capacitance is lower as can be inferred from this diagram 2 Phase CCD Single phase CCD Hynacek 1981 2 phase CCD The signs indicate addition of dopants opposite type as substrate by implantation These increase the surface potential to create the stepped potential Here the gate voltage on the second phase is dc phase one goes above and below the phase two voltage to move the charge packet In this figure we use an implantation imitate a dc voltage on the phase 2 gate This allows us to remove the phase 2 gate altogether Idea When Vg3 is applied the surface is accumulated and therefore the surface potential is approximately constant This situation simulates a gate voltage on the virtual phase Charge Transfer Efficiency This figure indicates schematically what happens when some charge is left behind this is dispersion Ref 11 J E Carnes and W F Kosonocky CCDs and Applications Solid State Tech 17 pp 67 77 1974 Signal Processing Applications Optical Signal Generation rear illumination Quantum efficiency is inversion charge generated per integrated photon flux F QI q Ft int See notes for details 1 R Ln 2 Ln 1 k cosh Ln k sinh Ln Ae T 1 Re T 1 e W Quantum efficiency is inversion charge generated per integrated photon flux F QI q Ft int The formula referred to in the figure is given on page 5 13 of the notes From Muller and Kamins Device Electronics for Integrated Circuits 2 ed Wiley 1986 Ref 10 N Teranishi et al IEEE TED ED 31 p 1829 1984 From Dueling Detectors in OEMagazine February 2002 by James Janesick of Sarnoff Corp FIGURE 1 A cross section of a CMOS pixel shows the four major functions required to generate an image FIGURE 2 A cross section of a CCD pixel shows the four major functions required to generate an image http oemagazine com FromTheMagazine feb02 detectors html PD no charge transfer Collection and read are at the same place PPD PG charge transfer is necessary CS charge transfer is necessary but is shared between collection and read areas Figure 8 Conventional photo diode PD pinned photo diode PPD photo gate PG and charge shared CS CMOS pixels The PD pixel architecture is the most popular pixel used in CMOS sensors The PG and CS pixels exhibit serious performance deficiencies as explained in text The PPD pixel is the highest performing CMOS pixel used in high end still camera applications The pixel requires custom implant processing to form the PPD region Janesick SPIE San Diego Focal Plane Arrays for Space Telescope paper 5167 1 Aug 2003 See also John Coghill Digital Imaging Technology 101 DALSA publication www dalsa com shared content PDFs Digital Imaging 101 Full Handout pdf Fairchild Imaging CCD 3041 The CCD 3041 is a 2k x 2k charge coupled device CCD full frame image sensor The CCD is intended for advanced scientific space medical industrial and commercial digital imaging applications The focal plane FPA is an array of 2048 horizontal by 2048 vertical imaging elements The pixel pitch is 15 m with a 100 fill factor For dark references each readout line is preceded by 16 dark pixels A multiport readout architecture has been adopted to accommodate high frame rates and low noise through four output ports Camera developers may also choose to clock the CCD through one or two outputs in order to simplify the drive electronics A single stage source follower output amplifier design was chosen for low noise performance The imager is available in a frontside as well as back illuminated configuration Source photonicsonline com Manufacturer Vision Research Inc The original Phantom v5 0 high speed digital imaging system was the first commercially available CMOS camera to offer rates of 1 000 pictures per second at 1024x1024 pixels Now updated to v5 1 this system s full frame speed increases to 1 200pps Gigabit Ethernet has been added and using new components and construction methods its size and weight have been slightly reduced The v5 1 continues to use the original high resolution sensor that this award winning system is famous for