Advanced MOS DevicesChapter 5: Charge-Coupled DevicesCullen College of EngineeringDepartment of Electrical and Computer EngineeringDr. Len TrombettaSpring 2011Idea: By alternating the relative size of 1, 2, charge can be moved to the right.We need some sort of read-out circuitry that will detect the charge when it gets to the end of the line.We “inject” charge by forward-biasing a diode; this is the “signal”.Bucket Brigade DeviceThis device can be used to delay a signal, which is useful for filtering applications.Charge-Coupled Device (CCD)We replace the source/drain idea with charge packets formed under an MOSC gate. Here the charge moves along the surface of the device (actually the Si-SiO2interface).Surface-Channel CCDThis is a “three-phase” CCD: three different potentials confine and move the charge. In this figure, the relative size of the potentials at adjacent gates is such that the charge is confined to the central gate.Here the charge moves below the surface, which keeps it away from interface states that would impede the flow or even capture charge, thus removing it from the signal.Bulk-Channel CCDDeep DepletionThe points A, B, C on the CV curve refer to the figures to the left.Increasing timeoxBoxISGCwqNCQVRelation between gate voltage, surface potential s, and inversion charge QI(Section 3.4.2.2)We need only the surface potential to indicate the extent to which the inversion layer has formed. The analogy with water in a well is clear.Fig. 3.8Note that VGis fixed; but QIis increasing with time, and hence sand w change.At a given gate voltage VG, if QIbecomes too large, the surface potential will not be able to confine the charge.In this figure, charge is intended to be confined under the gate labeled by 2.If the voltages on adjacent gates are VHand VL, the maximum charge we can store is)(max LHoxVVCQCharge is confined in the lateral direction by increasing the oxide thickness on either side of where the charge packet is to be stored.Thicker oxide moves the threshold voltage to larger values. Robert F. Pierret, “Semiconductor Device Fundamentals”, Addison-Wesley, 1996Higher doping density moves the threshold voltage to larger values.Electrical Signal Input Input gateA differential voltage is applied to gates VG1, VG2. The depth under this gate is then proportional to the signal. When the diode is forward biased, charge fills in proportion to the signal.The disadvantage to this structure is that capacitance is lower, as can be inferred from this diagram.Bulk-Channel CCD2-Phase CCDSingle phase CCD: Hynacek, 19812-phase CCD. The „+‟ signs indicate addition of dopants (opposite type as substrate) by implantation. These increase the surface potential to create the “stepped” potential.Here the gate voltage on the second phase is dc; phase one goes above and below the phase two voltage to move the charge packet.In this figure we use an implantation imitate a dc voltage on the phase 2 gate. This allows us to remove the phase 2 gate altogether.Idea: When Vg3 is applied, the surface is accumulated, and therefore the surface potential is approximately constant. This situation simulates a gate voltage on the virtual phase.Charge Transfer EfficiencyThis figure indicates schematically what happens when some charge is left behind; this is dispersion.Ref [11]: J. E. Carnes and W. F. Kosonocky, CCDs and Applications, Solid State Tech. 17, pp. 67-77, 1974Signal Processing ApplicationsOptical Signal Generation: rear illuminationWTTnnnneeReALkLkLLR11sinhcosh112int/FtqQIQuantum efficiency is inversion charge generated per integrated photon flux F.(See notes for details…)int/FtqQIQuantum efficiency is inversion charge generated per integrated photon flux F.The formula referred to in the figure is given on page 5-13 of the notes.From Muller and Kamins, Device Electronics for Integrated Circuits, 2 ed., Wiley 1986Ref [10]: N. Teranishi et al., IEEE TED ED-31, p. 1829 (1984)FIGURE 1 A cross-section of a CMOS pixel shows the four major functions required to generate an image.FIGURE 2 A cross-section of a CCD pixel shows the four major functions required to generate an image.http://oemagazine.com/FromTheMagazine/feb02/detectors.htmlFrom “Dueling Detectors” in OEMagazine February 2002 by James Janesick of Sarnoff Corp.Janesick, SPIE, San Diego, Focal Plane Arrays for Space Telescope, paper #5167-1, Aug 2003 Figure 8: Conventional photo diode (PD), pinned photo diode (PPD), photo gate (PG) and charge shared (CS) CMOS pixels. The PD pixel architecture is the most popular pixel used in CMOS sensors. The PG and CS pixels exhibit serious performance deficiencies as explained in text. The PPD pixel is the highest performing CMOS pixel used in high-end still camera applications. The pixel requires custom implant processing to form the PPD region.PD: no charge transfer. Collection and read are at the same place.PPD, PG : charge transfer is necessary.CS : charge transfer is necessary but is shared between collection and read areas.See also: John Coghill, Digital Imaging Technology 101; DALSA publication:www.dalsa.com/shared/content/PDFs/Digital_Imaging_101_Full_Handout.pdfThe CCD 3041 is a 2k x 2k charge coupled device (CCD) full frame image sensor. The CCD is intended for advanced scientific, space, medical, industrial and commercial digital imaging applications. The focal plane (FPA) is an array of 2048 horizontal by 2048 vertical imaging elements. The pixel pitch is 15µm with a 100% fill factor. For dark references, each readout line is preceded by 16 dark pixels. A multiport readout architecture has been adopted to accommodate high frame rates and low noise through four output ports. Camera developers may also choose to clock the CCD through one or two outputs in order to simplify the drive electronics. A single stage source follower output amplifier design was chosen for low noise performance. The imager is available in a frontside as well as back-illuminated configuration. Fairchild Imaging CCD 3041Source: photonicsonline.comThe original Phantom v5.0 high speed digital imaging system was the first commercially available CMOS camera to offer rates of 1,000 pictures per second at 1024x1024 pixels. Now updated to v5.1, this system's full frame speed increases to 1,200pps, Gigabit Ethernet has been added, and using new components and construction methods, its size and weight have been slightly reduced. The v5.1 continues to use the original high-resolution sensor