HOT CARRIERS AND RELIABILITY IN MOS DEVICES The term hot carriers refers to electrons or holes in the substrate of a MOS device that have energies significantly above average Hot carriers may be present due to a variety of circumstances When they are produced as a result of very high fields in the drain region of a MOSFET they may compromise operation of the device by generating charged defects in the oxide layer and by degrading the oxide and the Si SiO2 interface These effects constitute a reliability problem Hot carriers also generate unwanted current components References Sabnis VLSI Reliability in VLSI Electronic Microstructure Service vol 22 Academic Press N Y 1990 Chapter 6 Yue Reliability in ULSI Technology C Y Cheng and S M Sze eds Mc Graw Hill N Y 1996 Chap 12 Chenming Hu Hot carrier Effects in VLSI Electronic Microstructure Science Vol 18 Academic Press N Y 1989 Chapter 3 HOT CARRIER GENERATION We consider here the process of hot carrier generation near the drain Muller and Kamins Fig 10 9 Processes listed in Fig 10 9 1 Injection of electrons into the gate 2 Avalanche pair production 3 Substrate current Isub which can generate a voltage in competition with VBS 1 4 Forward biasing of source due to voltage drop caused by drift of holes from process 2 5 Collection of electrons emitted from source Processes 2 4 and 5 may become self sustaining in which case we have Avalanche Breakdown Process 4 is essentially DIBL where the field generated by VDS is sufficient to reduce the barrier to injection of electrons from the source Process 5 is punch through Avalanche Breakdown at the Drain For large VDS we risk avalanche breakdown at the drain Technically this is a hot carrier effect since avalanching requires high electric fields Note that an increase in NB will reduce the breakdown voltage Tsividis Fig 4 23 Snapback Breakdown An interesting effect arising from hot carrier generation near the drain is snapback breakdown Pierret Advanced MOS Fig 6 16 6 17 Mechanism Avalanche breakdown in the drain along with generation of substrate bias via hole drift through the substrate see Figure above Circuit model of Fig 6 17 suggests that we have a floating base BJT which is unstable and for which snapback breakdown in well known For the BJT the progression to breakdown is as follows See D K Schroder Advanced MOS Devices for further details Collector current for IB 0 is I C I E I CBO I C I CBO With avalanche multiplication at the drain this current is increased by a multiplication factor M 2 I C M I C I CBO Solving for IC gives IC MI CBO 1 M Thus IC gets very large i e we have avalanche breakdown when M 1 Since is not much less than 1 M is not very large unlike in a reverse bias pn junction where M must be very large for breakdown to occur The multiplication factor is related to the collector emitter voltage VCE and the breakdown voltage VBD by 3 M 1 1 VCE VBD m where m is a parameter that varies between 3 and 6 We can understand snapback as follows For low VCE M is 1 but M approaches 1 as VCE is increased Thus breakdown begins and a large IC flows But for BJTs increases as collector current goes up which means that M must decrease But a drop in M corresponds to a drop in VCE so as IC goes up VCE goes down In a MOSFET the formulation is different in detail but similar in concept For further information see F C Shu P K Ko S Tang C M Hu and R S Muller An Analytical Breakdown Model for Short Channel MOSFETs IEEE Trans Electron Dev ED 29 p 17351740 1982 These authors show that for the MOSFET case the relation between source drain current IS ID and M is IS M 1 I V D BS 0 65 R 1 1 kM k and the multiplication factor M becomes large as follows M 1 k 1 k In these equations k is the fraction of electrons collected by the drain that cause breakdown and R is the sum of substrate and external resistances MOSFET OXIDE DEGRADATION An important issue that we will discuss in detail is the trapping of charge in the oxide layer due to process 1 and generation of oxide charge and interface traps as a result This is an issue of oxide and Si SiO2 interface reliability ULSI Technology Figs 3 4 For now we simply point out that for very high electric fields near the drain or elsewhere electrons can enter the oxide via Fowler Nordheim tunneling FNT In this process electrons enter the oxide conduction band by tunneling through a reduced thickness energy barrier created by application of a high gate voltage This happens in measurable amounts for electric fields VG dox larger than 6 MV cm Effects of hot carrier injection HCI are measured for MOSFETs in terms of a degradation in transconductance gm or in mobility These effects are measured as changes in ID VD curves 4 n MOSFET Degradation Due To HCI Oxide charging and interface trap generation cause degradation in mobility or transconductance gm reduced ID reduced speed shift in threshold voltage Engineering Model Based on a review by C Hu in VLSI Electronics Microstructure Science we outline a phenomenological model of HCI induced MOSFET degradation Important parameters that correlate with hot carrier generation are Isub and Ig substrate and gate current VLSI Electronics Microstructure Science Figs 11 22 Define the following parameters 5 6 it critical energy to generate an interface trap i critical energy for impact ionization Te electron temperature d dt rate of degradation of some parameter e g VT gm G a function describing the dependence of the degradation mode on defects already present i e in the as fabricated device The model is I d A1 d G e it kTe dt W I sub A2 I d e i kTe Re arranging e i kTe I sub I d A2 1 k I 1 ln sub Te i I d A2 Substituting into the expression for d dt gives I d A1 G d e it k k i ln dt W I I A1 G d sub W I d A2 it i or I I d BG d sub dt W Id it i where B A1 A2 is a constant If we assume a specific form for G we can take this a step further We take G k Then 7 d B k I d I sub W I d it i dt I I it i B d sub W I d t 1 1 k Device a device lifetime t as the point at which reaches some failure criterion e g VT VT o 10 Then I I d sub W Id it i C I I d sub W Id it i This development relies on a great many assumptions and simplifications of the physics of highenergy electrons but provides an engineering model …