10-1 10 CMOS and SEMICONDUCTOR MEMORY 10.1 COMPLEMENTARY MOS (CMOS) Reference Chang and Sze, ULSI Technology, Section 9.3; Pierret, Modular Series on Solid State Devices: Advanced MOS Devices. Idea Power dissipation can be substantially reduced (and therefore packing density increased) if nMOS and pMOS devices are used together. We illustrate the case for digital logic using the inverter (the inverter is the proto-typical digital logic gate). Schroder, Advanced MOS, Fig. 5.4 In this figure, we have... - vi HI  T1 ON, T2 OFF  vout LO - vi LO  T1 OFF, T2 ON  vout HI Note that there is only a brief time during which both devices are ON,  very little power dissipation. HI - LO Transition (Fig. 5.4 d) Note that for vout HI, VS(T2) ~ VDD, and VGS(T2) = - VDD. To get T2 OFF, we need vi = VDD - VT2. 10.1.1 CMOS Fabrication Issues We can fabricate CMOS using - n substrate with p-wells - p substrate with n-wells - twin wells (twin tubs) - this is the case for most modern processing schemes Wolf, Fig. 8-1 CMOS Well Parameters Parasitic Capacitance Well doping is higher than background typically, so S/D capacitance is generally higher. Thus, if more of one device than another (nMOS vs. pMOS) will be made, it is advantageous to put the less-frequently occurring type in the well. If equal numbers of nMOS and pMOS (which is the case for CMOS), note that (pMOS) < (nMOS), so make W/L (pMOS) > W/L (nMOS) to keep current drive up.10-210-3 Vertical Isolation Need to avoid punch through between S/D depletion regions and substrate. This can be done with higher well doping, which at the surface may be undesirable for mobility reasons. - Solution Retrograde well results in good vertical isolation and less extreme surface doping (see Fig. 16 below). Note the surface p-layer doping, which is a VT adjust. Wolf, Fig. 8-12 10.1.2 Latch-Up in CMOS Devices Latch-up is a condition in which high currents can be generated between VDD and VSS. These currents are induced by a variety of transient phenomena and persist even when the transient decays; thus the device “latches-up”. The mechanism involves parasitic BJT action. Sze, VLSI Technology, Fig. 27 Sequence i. vout < VSS by 0.7 V (via transient event, e.g., voltage spike or radiation single event upset)  electrons injected into p-tub from n+ drain. ii. n-substrate acts as a collector of npn parasitic BJT, so electrons drift to VDD. iii. If electron current and resistance are large such that iR ~ 0.7 V, p source will inject holes into n-substrate. Then, holes enter p-tub which acts as collector; holes drift to VSS. iv. If iR is large, n source will be induced to inject electrons into the p-tub. v. Electrons are collected at VDD. Positive feedback is established  saturation occurs. Latch-up continues until VDD or VSS is disconnected. Preventing Latch-Up Latch-up requires... - sufficient gain in parasitic BJTs and - sufficient resistance in substrate and p-tub to induce iR ~ 0.7 Volts. Thus tendency to latch-up can be reduced by... - SOI (Silicon-on-Insulator – See Chapter 8) - use of epitaxial substrate, e.g. p/p+ for n-well and n/n+ for p-well. - using guard rings around FETs to divert minority carriers. - high-dose, high energy implants to reduce BJT gain10-410-5 10.2 PSPICE SPICE (Simulation Program with Integrated Circuit Emphasis) and its derivatives (including PSPICE [the “P” indicates that the program can run on a personal computer]) have, in the basic package, three levels of MOSFET simulation. The first is the most simple, and allows basic calculations using text-book models of MOSFETs. Levels 2 and 3 include secondary effects, such as mobility modulation and channel length modulation. Some specifics: Level 1: Square Law model; channel length modulation parameter  can be specified. Level 2: Bulk Charge model; if  is not specified, a simple depletion approximation model is used to determine L. Level 3: Numerical approximations to the Bulk Charge model are made in an effort to improve computation time. Level 3 is similar to Level 2 as far as channel length modulation. Other PSPICE parameters: - NSS, NFS: Surface State Density and Fast Surface State Density. These are areal densities of what we called fixed charge Qf/q and interface traps Qit/q. - UCRIT, UEXP: Level 2 mobility degradation model. Recall from Chapter 7 that one of our models for mobility degradation was expUeffCritOeff - THETA: Level 3 mobility degradation model. From Chapter 7 another mobility model was )(1TGOeffVV  - LAMDA: Channel length modulation - GAMMA: Body bias parameter (called Bulk Threshold Parameter in PSPICE) - VTO: Threshold voltage with no body bias (called Zero Bias Threshold Voltage in PSPICE) Level 4 and beyond: Accurate modeling of sub-micron MOSFETs was introduced with BSIM (Level 4) and later BSIM2 and BSIM3 (as of this writing the most recent version is BSIM3v3). An attempt is made to incorporate some of the small device modeling that was covered in Chapter 7, including velocity saturation, DIBL, mobility degradation, non-uniform channel doping, and subthreshold characteristics. BSIM is a semi-empirical approach, attempting to get the physics right while using parameterization and some curve-fitting to reduce computation time. In the words of Wolfe, Section 5.5: Terms with strong physical meaning are employed to model the fundamental physical effects while empirically derived parameters are judiciously used ot embrace less-well-understood and generally subtle) device characteristics.10-6 As a result, the mapping of parameters to what we have done in Chapter 7 is difficult. The interested reader is referred to the references below. References - Shichman and Hodges, Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits, IEEE Journal of Solid State Circuits SC-3 (3), p. 288 (1968) - Sheu, Scharfetter, Ko, and Jeng, BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors, IEEE Journal of Solid State Circuits SC-22 (4), p. 558 (1987) 10.3 MOSFET MEMORY References - Pierret, Advanced MOS Devices, Chapter 5 - E. Maes, G. Groesenekar, H. Lebon, and J. Witters, Trends in Semiconductor Memories, Microelectronics Journal 20 (1-2), 9 (1989) 10.3.1 Memory Types - Random Access Memory (RAM) - Dynamic RAM (DRAM) - Static RAM (SRAM) - Read Only Memory (ROM) - Programmable ROM