Advanced MOS Devices Chapter 8 Ultra Small MOSFETs Performance Fabrication and Materials Issues Cullen College of Engineering Department of Electrical and Computer Engineering Dr Len Trombetta General Scaling Considerations Yuan Taur et al CMOS Scaling into the Nanometer Regime Proc IEEE 85 4 486 1997 Gate current Oxide tunnel current is a power dissipation problem as well as a reliability problem Yuan Taur et al 1997 Poly Depletion At high vertical fields the depletion region in the poly gate adds capacitance poly gate is in series so total capacitance is reduced Quantum Mechanics Channel Doping Variation The number of dopants in the channel will begin to show statistical variation that can shift VT The figure is based on simulations using a 3D drift diffusion model FIELDAY Principal results L 100 nm W 50 nm tox 3 nm average NB 8 6 x 1017 cm 3 spread in IV 20 30 mV average shift 50 mV subthreshold and 15 mV linear slight degradation and variability of subthreshold slope This figure is from Taur et al 1997 The original work was from Wong and Taur 1993 IEDM Tech Dig pg 705 Low T 0 1 m MOSFET Idea Velocity saturation in small devices no increase in performance with increase in power dissipation Therefore we need to reduce voltage levels which means low T operation Lithography Direct write e beam Performance 77 K 0 1 m device gm 760 mS mm 300 K device functions but less well than at 77 K Smallest Device L 0 07 m 700 G A Sai Halasz et al Design and Experimental Technology for 0 1 m Gate Length Low T Operation FETs IEEE Electron Device Lett EDL 8 10 463 1987 Silicon mobility vs temperature 77 K 300 K Electron mobility versus temperature for different doping levels 1 High purity Si Nd 1012 cm 3 time of flight technique Canali et al 1973 2 High purity Si Nd 4 1013 cm 3 photo Hall effect Norton et al 1973 3 Nd 1 75 1016 cm 3 Na 1 48 1015 cm 3 Hall effect Morin and Maita 1954 4 Nd 1 3 1017 cm 3 Na 2 2 1015 cm 3 Hall effect Morin and Maita 1954 http www ioffe rssi ru SVA NSM Semicond Si electric html 0 1 m Devices at Low Temperature 300 K 77 K G A Sai Halasz et al IEEE Electron Device Letters EDL 8 10 463 1987 0 04 m Devices Toshiba 1995 H Iwai et al Microelectronic Engineering 28 147 1995 H Iwai et al Microelectronic Engineering 28 147 1995 Substrate current Isub is an indication that hot electron effects are taking place this is a reliability issue H Iwai et al Microelectronic Engineering 28 147 1995 Sub 0 03 m Devices CEA LETI 2004 G Bertrand et al Towards the limits of conventional MOSFETs case of sub 30 nm NMOS devices Solid State Electronics 48 4 505 2004 Current still improves with decreasing Lg Transconductance is poor for small Lg unless Rsd can be controlled No velocity overshoot is observed G Bertrand et al Towards the limits of conventional MOSFETs case of sub 30 nm NMOS devices Solid State Electronics 48 4 505 2004 Sub 0 01 m Devices IBM Hopewell Junction These are SOI devices TSi 4 8 nm SiO2 150 nm B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 pFET with mild halo B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 nFET with mild halo B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 Effect of various halo treatments Halo implant changes VT which may be significant the ultra thin Si channel along with the strong halo impant condition is effective in suppressing the threshold voltage roll off B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 6 nm gate length pFET IDSAT is low possibly due to process induced variations coupled with the ultra thin Si layer in the channel and the S D extension regions B Doris et al Extreme Scaling with Ultra Thin Si Channel MOSFET IEDM Tech Digest 2002 267 Iwai 2004 Table 1 Predicted limitations for downsizing Time Frame Expected Limit Cause Late 1970 s 1 m Short channel effects Early 1980 s 0 5 m S D resistance Early 1980 s 0 25 m Gate oxide tunneling current Late 1980 s 0 1 m various Today 10 nm fundamental Potentially Limiting Issues see Iwai 2004 Performance Saturation current does not continue to scale with decreasing L Source drain tunneling current may be an issue below 10 nm Price Can we afford to improve the technology Power Based on current progress the chip surface gets as hot as a rocket nozzle in a few years Reliability Particulates can we keep the substrate clean Oxide defects breakdown High k Iwai Tokyo Inst Tech 2004 One method for getting around reduced performance Quantum Mechanics 101 Basic Postulate Everything is simultaneously a particle and a wave Schr dinger Wave Equation the solution is which is the state function for the particle an electron say Depending on q z be a simple sinusoid or a complex function of position h2 d 1 d q z Eij 2 4 2 dz mi z dz ij may z 0 The location of the particle can be found only in a statistical sense the probability that the electron is in a volume dV is dV In SWE q z is the potential energy seen by the electron For an MOS device this is the energy band structure Relation to devices A QM treatment becomes necessary when the electron wavelength is comparable to the device dimensions At device energies 10 s of Quantum Based models of MOSFETs Issues Gate oxide tunneling Inversion layer location and density h2 d 1 d q z Eij 2 4 2 dz mi z dz Schr dinger Wave Equation ij z 0 n p Poisson Equation d dz z d dz z q n z p z NA ND o The arrows indicate that we have a self consistent calculation in which SWE tells us the electron hole density which is plugged into Poisson which gives us a new estimate of the potential which goes back into SWE Maxwell Boltzmann charge carriers are classical particles Fermi Dirac Pauli exclusion holds QM wave particle duality holds The fact that charge is distributed away from the interface means that we need a larger gate voltage to have the same effect i e VT goes up S H Lo et al IBM J Research and Development Vol 43 p 327 1999 Oxide Modification Cl F and Deuterium Observation There have been reports of increased hot carrier resistance by addition of fluorine deuterium and chlorine to the oxidation ambient through a post oxidation anneal Mechanism Formation of Si F or Si Cl bonds at interface may be more resistant to de passivation Problems F and Cl must be carefully controlled since excess amounts result in oxide etching and degradation Also industry has not …