Advanced MOS DevicesChapter 8: Ultra-Small MOSFETs: Performance, Fabrication, and Materials IssuesCullen College of EngineeringDepartment of Electrical and Computer EngineeringDr. Len TrombettaYuan Taur et al., CMOS Scaling into the Nanometer Regime, Proc. IEEE 85 (4), 486 (1997)General Scaling ConsiderationsOxide tunnel current is a power dissipation problem as well as a reliability problem.Gate currentYuan Taur et al., (1997)At high vertical fields, the depletion region in the poly gate adds capacitance (poly gate is in series, so total capacitance is reduced).Poly DepletionQuantum Mechanics!!The number of dopants in the channel will begin to show statistical variation that can shift VT.Channel Doping VariationThis figure is from Taur et al (1997). The original work was from Wong and Taur, 1993 IEDM Tech Dig pg. 705 The figure is based on simulations using a 3D drift-diffusion model (FIELDAY). Principal results:L = 100 nm; W = 50 nm; tox= 3 nm; average NB= 8.6 x 1017cm-3• spread in IV: = 20-30 mV• average shift ~ -50 mV (subthreshold) and -15 mV (linear)• slight degradation and variability of subthreshold slopeLow-T 0.1 m MOSFETG. A. Sai Halasz et al., Design and Experimental Technology for 0.1 µm Gate-Length Low TOperation FETs, IEEE Electron Device Lett. EDL-8 (10), 463 (1987)Idea Velocity saturation in small devices no increase in performance with increase in powerdissipation. Therefore we need to reduce voltage levels, which means low T operation.Lithography Direct write e-beamPerformance77 K: 0.1 m device gm = 760 mS/mm300 K: device functions but less well than at 77 KSmallest Device L = 0.07 m = 700 ÅElectron mobility versus temperature for different doping levels.1. High purity Si (Nd< 1012cm-3); time-of-flight technique (Canali et al. [1973])2. High purity Si (Nd< 4·1013cm-3): photo-Hall effect (Norton et al. [1973])3. Nd= 1.75·1016cm-3; Na = 1.48·1015cm-3; Hall effect (Morin and Maita [1954]).4. Nd= 1.3·1017cm-3; Na = 2.2·1015cm-3; Hall effect (Morin and Maita [1954]). http://www.ioffe.rssi.ru/SVA/NSM/Semicond/Si/electric.htmlSilicon mobility vs. temperature.300 K77 K0.1 m Devices at Low TemperatureG. A. Sai-Halasz et al., IEEE Electron Device Letters EDL-8 (10), 463 (1987)300 K77 K0.04 m Devices (Toshiba 1995)H. Iwai et al., Microelectronic Engineering 28, 147 (1995)Substrate current Isubis an indication that “hot electron effects” are taking place; this is a reliability issue.H. Iwai et al., Microelectronic Engineering 28, 147 (1995)H. Iwai et al., Microelectronic Engineering 28, 147 (1995)G. Bertrand et al., Towards the limits of conventional MOSFETs: case of sub-30 nm NMOS devices, Solid State Electronics 48 (4), 505 (2004)Sub-0.03 m Devices (CEA-LETI 2004)G. Bertrand et al., Towards the limits of conventional MOSFETs: case of sub-30 nm NMOS devices, Solid State Electronics 48 (4), 505 (2004)• Current still improves with decreasing Lg• Transconductance is poor for small Lg unless Rsd can be controlled• No velocity overshoot is observedTSi4 – 8 nmSiO2150 nmB. Doris et al., Extreme Scaling with Ultra-Thin Si Channel MOSFET, IEDM Tech Digest 2002, 267 Sub-0.01 m Devices (IBM Hopewell Junction)These are “SOI” devices…B. Doris et al., Extreme Scaling with Ultra-Thin Si Channel MOSFET, IEDM Tech Digest 2002, 267 pFET with “mild halo”nFET with “mild halo”B. Doris et al., Extreme Scaling with Ultra-Thin Si Channel MOSFET, IEDM Tech Digest 2002, 267Effect of various halo treatments“…the ultra-thin Si channel along with the strong halo impant condition is effective in suppressing the threshold voltage roll-off.”Halo implant changes VT, which may be significant.B. Doris et al., Extreme Scaling with Ultra-Thin Si Channel MOSFET, IEDM Tech Digest 2002, 2676 nm gate length pFETIDSAT is low, possibly due to “process-induced variations coupled with the ultra-thin Si layer in the channel and the S/D extension regions.”B. Doris et al., Extreme Scaling with Ultra-Thin Si Channel MOSFET, IEDM Tech Digest 2002, 267Time Frame Expected Limit CauseLate 1970’s 1 m Short channel effectsEarly 1980’s 0.5 m S/D resistanceEarly 1980’s 0.25 m Gate oxide tunneling currentLate 1980’s 0.1 m variousToday 10 nm fundamental?Iwai 2004 Table 1: Predicted limitations for downsizingPotentially Limiting Issues (see Iwai, 2004)• Performance• Saturation current does not continue to scale with decreasing L.• Source – drain tunneling current may be an issue below 10 nm.• Price• Can we afford to improve the technology?• Power• Based on current progress, the chip surface gets as hot as a rocket nozzle in a “few years”.• Reliability• Particulates – can we keep the substrate clean?• Oxide defects/breakdown• High-kIwai (Tokyo Inst. Tech. 2004)One method for getting around reduced performance…Quantum Mechanics 101Basic Postulate: Everything is simultaneously a particle and a wave.Schrödinger Wave Equation: the solution is , which is the “state function” for the particle (an electron, say). Depending on q (z), may be a simple sinusoid or a complex function of position.0)()()(142*22zEzqdzdzmdzdhijijiIn SWE, q (z) is the potential energy seen by the electron. For an MOS device, this is the energy band structure.The location of the particle can be found only in a statistical sense: the probability that the electron is in a volume dV is = dV.Relation to devices: A QM treatment becomes necessary when the electron wavelength is comparable to the device dimensions. At device energies, ~ 10’s of Å.Quantum – Based models of MOSFETsIssues:• Gate oxide tunneling• Inversion layer location and density0)()()(142*22zEzqdzdzmdzdhijijiDAoNNzpznqzdzdzdzd)()()()(Schrödinger Wave Equation:Poisson Equation:pn,The arrows indicate that we have a “self-consistent calculation” in which SWE tells us the electron /hole density, which is plugged into Poisson, which gives us a new estimate of the potential, which goes back into SWE…S.-H. Lo et al., IBM J. Research and Development, Vol. 43, p 327, (1999)Maxwell-Boltzmann: charge carriers are classical particlesFermi-Dirac: Pauli exclusion holdsQM: wave-particle duality holdsThe fact that charge is distributed away from the interface means that we need a larger gate voltage to have the same effect; i.e., VTgoes up.Oxide Modification: Cl, F, and Deuterium• Observation There have been reports of increased hot carrier resistance by addition of fluorine,