UH ECE 6347 - Chapter 10- CMOS, PSPICE, and Memory

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Advanced MOS Devices Chapter 10: CMOS, PSPICE, and Memory Cullen College of Engineering Department of Electrical and Computer Engineering Dr. Len TrombettaCMOSCMOS ProcessingRetrograde Well We need heavy doping below the active area to avoid punch-through to the substrate, and lighter doping near the surface (mobility issue; threshold adjust). So do ion implant and brief anneal. Conventional process: diffusion only p-well n-wellLatch-Up Sze, VLSI Technology Initiating Latch-Up • Spurious drop at output to VSS - 0.7 V causes e- injection into p-tub from n+ drain; • Electrons collected at VDD, and cause 0.7 V rise, which injects holes from p+ source; • Holes collected at VSS, and voltage drop reinforces electron injection from n+ drain. Controlling Latch-Up • SOI (Silicon-on-Insulator – See Chapter 8) • Use of epitaxial substrate, e.g. p/p+ for n-well and n/n+ for p-well. • Using guard rings around FETs to divert minority carriers. • High-dose, high energy implants (retrograde well) to reduce BJT gain Problem: Conducting path established from VSS to VDDLevel 1: Square Law model; channel length modulation parameter l can be specified. Level 2: Bulk Charge model; if l is not specified, a simple depletion approximation model is used to determine DL. Level 3: Numerical approximations to the Bulk Charge model are made in an effort to improve computation time. Level 3 is similar to Level 2 as far as channel length modulation. Level 4+ (BSIM): Terms with strong physical meaning are employed to model the fundamental physical effects while empirically derived parameters are judiciously used to embrace less-well-understood (and generally subtle) device characteristics. (Wolfe, Section 5.5) PSPICE OverviewexpUeffCritOeff)(1TGOeffVV -NSS, NFS: Surface State Density and Fast Surface State Density - fixed charge Qf/q and interface traps Qit/q -THETA: Level 3 mobility degradation model. -LAMDA: Channel length modulation -GAMMA: Body bias parameter (called Bulk Threshold Parameter in PSPICE) -VTO: Threshold voltage with no body bias (called Zero Bias Threshold Voltage in PSPICE) -UCRIT, UEXP: Level 2 mobility degradation model Sample of PSPICE ParametersPSPICE Simulations…• Random Access Memory (RAM) • Dynamic RAM (DRAM) • Static RAM (SRAM) • Read Only Memory (ROM) • Programmable ROM (PROM) • Electrically-Erasable Programmable ROM (E2PROM) • Flash EEPROM • NOR • NAND Generic Memory Types MOSFET Memory Pierret, Advanced MOS Chapter 5SRAM • Large area • High power dissipation (one “leg” always connects VDD to ground.) Issues:CMOS SRAM Power is dissipated only during switching: P = CV2f • Large area • Low power dissipation (no path connects VDD to ground.)DRAMSchemes for Increasing DRAM Capacitance Acceptor doping increases capacitance, but not stored charge because difference in fs is less. Near-surface donor doping increases fs (looks like a gate voltage). Maes 1989Non-Volatile Memory: General Scheme Burns and BondNon-Volatile Memory: Early Ideas Muller and KaminsFlash NOR Architecture . . .Bit LineWord Line 1Word Line 2Word Line 16NOR: 1 FET per bit line • Full access to address and data buses • Number of read/write cycles is low • Useful in BIOS and firmwareFlash NAND Architecture NAND: 16 serially connected FETs . . .Bit LineSelect GateDrainWord Line 1Word Line 2Word Line 3Word Line 16Select GateSource• Not fully addressable; block read • Number of read/write cycles is higher than NOR • Useful in mass storage to replace hard drivesFLASH Bez Energy band diagram showing flat bands (no charge on floating gate) and charged state. VT shift induced by charging of floating gate.Programming via Channel Hot Electron Injection n+ drain n+ source Floating gate Control gate substrate “Channel Hot Electron Injection” is used to program cells in the NOR technology. High electric fields near drain cause injection to floating gateProgram/Erase via FNT Injection Poly Si SiO2 f = 3.1V f = 4V FNT to substrate is used for program and erase in NAND. drain source Floating gate Control gate substrate FNT to source contact is used for erase in NOR.Flash Reliability Issue This can be handled in software by verifying and extending p/e time, but this gets prohibitive. VT for program and erase begin to approach one another after many p/e cycles. Problem: Interface state generation and charge trapping near drain !!! * Initial decrease is due to anomalous positive charge !!! *VT Distribution: SILC Problem Typical distribution is Gaussian (straight line fit) with a low-VT tail. Devices in the tail increase after stressing, due to SILC, for 8 nm oxide. Slightly thicker oxide improves the situation dramatically.Program Disturb Mechanisms gnd VG gnd gnd gnd gnd gnd gnd gnd


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