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Aihara, “Chaos and asymptotical stability in dis-crete-time neural networks,” Physica D, vol. 104, pp. 286–325, 1997.[21] G. Chen, S.-B. Hsu, and J. Zhou, “Snapback repellers as a cause ofchaotic vibration of the wave equation with a van der Pol boundary con-dition and energy injection at the middle of the span,” J. Math. Phys.,vol. 39, pp. 6459–6489, 1998.[22] E. Bollt, “Stability of order: An example of chaos “near” a linear map,”Int. J. Bifurcat. Chaos, vol. 9, no. 10, pp. 2081–2090, 1999.Clock-Gating and Its Application to Low Power Designof Sequential CircuitsQing Wu, Massoud Pedram, and Xunwei WuAbstract—This paper models the clock behavior in a sequential circuitby a quaternary variable and uses this representation to propose and an-alyze two clock-gating techniques. It then uses the covering relationshipbetween the triggering transition of the clock and the active cycles of var-ious flip flops to generate a derived clock for each flip flop in the circuit. Atechniqueforclockgatingisalsopresented,whichgeneratesaderivedclocksynchronous with themaster clock.Design examples using gated clocks areprovidednext.Experimentalresultsshowthatthesedesignshaveideallogicfunctionality with lower power dissipation comparedto traditional designs.Index Terms—Clock gating, CMOS, logic, low power, sequential circuit,synthesis.I. INTRODUCTIONThe sequential circuits in a system are considered major contributorsto the power dissipation since one input of sequential circuits is theclock, which is the only signal that switches all the time. In addition,the clock signal tends to be highly loaded. To distribute the clock andcontrol the clock skew, one needs to construct a clock network (oftena clock tree) with clock buffers. All of this adds to the capacitance ofthe clock net. Recent studies indicate that the clock signals in digitalcomputers consume a large (15–45%) percentage of the system power[1]. Thus, the circuit power can be greatly reduced by reducing theclock power dissipation.Manuscript received September 7, 1997; revised January 29, 1999. This workwas supported in part by DARPA under Contract F33615-95-C-1627 and in partby the NNSF of China under Grant 69773034. This paper was recommended byAssociate Editor M. GlessnerQ. Wu and M. Pedram are with the Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA 90089 USA.X. Wu is with the Institute of Circuits and Systems, Ningbo University,Ningbo, Zhejiang 315211, China.Publisher Item Identifier S 1057-7122(00)02319-9.Most efforts for clock power reduction have focused on issues suchas reduced voltage swings, buffer insertion, and clock routing [2]. Inmany cases, switching of the clock causes a great deal of unnecessarygate activity. For that reason, circuits are being developed with con-trollable clocks. This means that from the master clock other clocksare derived which, based on certain conditions, can be slowed down orstopped completely with respect to the master clock. Obviously, thisscheme results in power savings due to the following factors.1) The load on the master clock is reduced and the number of re-quired buffersin the clock tree is decreased. Therefore, the powerdissipation of clock tree can be reduced.2) The flip flop receiving the derived clock is not triggered in idlecycles and the corresponding dynamic power dissipation is thussaved.3) The excitation function of the flip flop triggered by the derivedclock may be simplified since it has a do not care condition inthe cycle when the flip flop is not triggered by the derived clock.The clock-gating problem has been studied in [3]–[5]. In [3] the au-thors presented a technique for saving power in the clock tree by stop-ping the clock fed into idle modules. However, anumber of engineeringissues related to the design of the clock tree were not addressed and,hence, the proposed approach has not been adopted in practice. In [4], aprecomputation-based technique is used to generate a signal to controlthe load enable pin of the flip flops in the data path. The control signalis derived by investigating the relationship between the latched inputand the primary outputs of the combinational blocks in the data path.The technique is useful only if the outputs of the block can be precom-puted (predicted) for certain input assignments. In [5], the authors usea latch to gate the clock in control-dominated circuits. The problem isthat the additional latch receives the clock’s triggering signal, which re-sults in extra power dissipation in the latch itself. Besides, this schemeresults in the derived clock having a considerable skew with respect tothe master clock.This paper investigates various issues in deriving a gated clock froma master clock. In Section II, a quaternary variable is used to modelthe clock behavior and to discuss its triggering action on flip flops.Based on this analysis, two clock-gating schemes are proposed. In Sec-tion III, we use the covering relation between the clock and the transi-tion behaviors of the triggered flip flops to derive conditions for gatingthe master clock. Two common sequential circuits, i.e., 8421 BCDcode up-counter and three-excess counter, are then described to illus-trate the procedure for finding a derived clock. In Section IV, a newtechnique for clock gating is presented which generates a clock syn-chronous with the master clock. This eliminates the additional skewbetween the master clock and the