1The New Era of Scaling in an SoC WorldMark BohrIntel Senior FellowLogic Technology Development2009 ISSCC2The End of Scaling is Near?“Optical lithography will reach its limits in the range of 0.75-0.50 microns”“Minimum geometries will saturate in the range of 0.3 to 0.5 microns”“X-ray lithography will be needed below 1 micron”“Minimum gate oxide thickness is limited to ~2 nm”“Copper interconnects will never work”“Scaling will end in ~10 years”Perceived barriers are meant to be surmounted, circumvented or tunneled through3Outline• Transistor Scaling• Microprocessor Evolution• Vision of the Future40.010.11101970 1980 1990 2000 2010 2020MicronsCPU Transistor Count2x every 2 years103105109107Scaling TrendsTransistor dimensions scale to improve performance,reduce power and reduce cost per transistor50.010.11101970 1980 1990 2000 2010 2020Microns45nm65nm32nmFeature Size0.7x every 2 yearsCPU Transistor Count2x every 2 years103105109107Scaling TrendsTransistor dimensions scale to improve performance,reduce power and reduce cost per transistor6MOSFET ScalingR. Dennard, IEEE JSSC, 1974Device or Circuit Parameter Scaling FactorDevice dimension tox, L, W 1/κDoping concentration Na κVoltage V 1/κCurrent I 1/κCapacitance εA/t 1/κDelay time/circuit VC/I 1/κPower dissipation/circuit VI 1/κ2Power density VI/A 1Classical MOSFET scaling was first described in 1974730 Years of MOSFET ScalingGate Length: 1.0 µm 35 nmGate Oxide Thickness: 35 nm 1.2 nmOperating Voltage: 4.0 V 1.2 V1 µmDennard 1974 Intel 2005Classical scaling ended in the early 2000s due to gate oxide leakage limits890 nm Strained Silicon TransistorsHighStressFilmNMOSSiGe SiGePMOSSiN cap layer SiGe source-drainTensile channel strain Compressive channel strainStrained silicon provided increased drive currents, making up for lack of gate oxide scaling9High-k + Metal Gate Transistors65 nm Transistor 45 nm HK+MGHigh-k + metal gate transistors break through gate oxide scaling barrierSiO2dielectric Hafnium-based dielectricPolysilicon gate electrode Metal gate electrode1011010010000.4 0.6 0.8 1.0 1.2 1.4 1.6ION (mA/um)IOFF (nA/um)1.0 V65nm 45nm11010010000.6 0.8 1.0 1.2 1.4 1.6 1.8ION (mA/um)IOFF (nA/um)1.0 V65nm 45nm+12% +50%NMOS PMOS100x5xTransistor Performance Increase45 nm HK+MG provides average 30% drive current increase or >5x IOFFleakage reductionRef. K. Mistry, IEDM ’0711Gate Leakage ReductionHK+MG significantly reduces gate leakage 0.000010.00010.0010.010.1110100-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2VGS (V)N o rm a liz e d G a te L e a k a g eSiON/Poly 65nm HiK+MG 45nmNMOS PMOS HiK+MG 45nmSiON/Poly 65nm 25x1000x1202468101265nm 45nmNormalized Cell LeakageIGATEIOFFIJUNCT1.0V 25C10xBitcell Leakage ReductionSRAM bitcell leakage reduced ~10x130.40.50.60.70.80.911.1180nm 130nm 90nm 65nm 45nmMinimal oxide scale HiK+MGTox scalingVTVariability Reduction(21242443⋅=⋅⋅⋅=ZeffLeffcZeffLeffNTqVoxoxBsiTranεφεσHK+MG provides oxide scaling needed for variability reductionRef. K. Kuhn, IEDM ’07C2Normalized to 180nmC2Less VTvariation140.1110500 350 250 180 130 90 65 45 32Technology Generation (nm)M2 Pitch (um)0246810# MetalLayersInterconnect TrendsAdded metal layers + material improvements enable interconnect scaling0.7x per generation150.1110500 350 250 180 130 90 65 45 32Technology Generation (nm)M2 Pitch (um)0246810# MetalLayersInterconnect TrendsAdded metal layers + material improvements enable interconnect scaling0.7x per generation160.1110500 350 250 180 130 90 65 45 32Technology Generation (nm)M2 Pitch (um)0246810# MetalLayersInterconnect TrendsAdded metal layers + material improvements enable interconnect scalingAl CuLower-kSiO2SiOF Low-k1745 nm InterconnectsM8 810M7 560M6 360M5 280M4 240M3 160M2 160M1 160Low-kCuLoose pitch + thick metal on upper layers• High speed global wires• Low resistance power grid Tight pitch on lower layers• Maximum density for local interconnectsHierarchical interconnect pitchesPitch (nm)1845 nm InterconnectsM97 µm CuPolymer M1-8Thick M9 for very low resistance on-die power routing1945 nm Microprocessor Products45 nm process serves microprocessor applicationsfrom low power to high performanceSingle Core6 CoreDual Core8 CoreQuad Core200.010.11101970 1980 1990 2000 2010 2020Microns32nm32 nm Generation2132 nm Logic Technology• 2ndgeneration high-k + metal gate transistors- High-k EOT scaled from 1.0 nm to 0.9 nm- Replacement metal gate process flow- 4thgeneration strained silicon• 9 copper + low-k interconnect layers- Hierarchical interconnect pitches- Thick M9 for power routing• Immersion lithography on critical layers- 70% transistor and interconnect pitch scaling- 50% SRAM cell area scaling• Pb-free and halogen-free packagesHigher performance, lower power, lower cost per transistor2210010001995 2000 2005 2010Gate Pitch (nm)0.7x every 2 yearsPitchPitchPitchContacted Gate Pitch TrendTransistor gate pitch continues to scale 0.7x every 2 years32 nm Generation112.5 nm Pitch230.00.51.01.52.01001000Gate Pitch (nm)Drive Current (mA/um)0.00.51.01.52.01.0 V, 100 nA IOFF45nm32nm65nm90nmNMOSPMOS130nmTransistor PerformanceDrive currents continue to increase while gate pitch scales2432 nm InterconnectsHierarchical interconnect pitchesM9M8 566.5M7 450.1M6 337.6M5 225.0M4 168.8M3 112.5M2 112.5M1 112.58 um Cu Pitch (nm)250.11101995 2000 2005 2010Cell Area (um2)0.5x every 2 yearsSRAM Cell Size ScalingTransistor density continues to double every 2 years32 nm Generation0.171 um2Cell26SRAM Cell Scaling65 nm 0.570 µm245 nm 0.346 µm232 nm 0.171 µm2Good pattern resolution while scaling feature size and continuing with 193 nm exposure wavelength2732 nm SRAM Test Chip• 291 Mbit• 0.171 um2cell size• >1.9 billion transistors• >3.8 GHz operation• Functional silicon in Aug ‘0732 nm SRAM test vehicle included all transistor and interconnect features used on 32 nm microprocessorsRef. Y. Wang, paper 27.1, ISSCC ’092830 Years of ScalingContact 1978Ten 32nm SRAM Cells 20081 µm29The Old Era of Device ScalingIt has served us well for >30 yearsDevice or Circuit Parameter Scaling FactorDevice dimension tox, L, W 1/κDoping concentration Na κVoltage V 1/κCurrent I 1/κCapacitance εA/t 1/κDelay time/circuit VC/I 1/κPower dissipation/circuit VI 1/κ2Power density VI/A 130The New Era of Device ScalingModern CMOS scaling is as much