Slide 1Chapter OutlineArguments for Sleep Mode ManagementStandby Power - Was Not A Concern In Earlier DaysDynamic Power - Clock GatingClock GatingClock-gating Efficiently Reduces PowerClock GatingClock Hierarchy and Clock GatingTrade-Off between Sleep-Modes and Sleep-TimeSleep Modes in mProcessors and mControllersThe Standby Design Exploration SpaceAlso the Case for Peripheral DevicesThe Leakage Challenge – Power in StandbyStandby Static Power Reduction ApproachesTransistor StackingTransistor StackingForced Transistor StackingPower GatingPower Gating ─ ConceptPower Gating OptionsOther option: Boosted-Gate MOS (BGMOS)Other Option: Boosted-Sleep MOSVirtual SuppliesDecoupling Capacitor PlacementSlide 26How to Size the Sleep Transistor?Sleep Transistor SizingPreserving StateLatch Retaining State during SleepMTCMOS Derivatives Preventing State LossSleep Transistor PlacementSleep Transistor LayoutDynamic Body BiasingDynamic Body BiasingThe Dynamics of Dynamic Body BiasBody Bias LayoutDBB for Standby Leakage Reduction - ExampleEffectiveness of Dynamic Body BiasingSupply Voltage Ramping (SVR)Supply RampingSupply Ramping ─ ImpactIntegration in Standard Cell Layout MethodologyStandby Leakage Management ─ A ComparisonSome Long-Term MusingsSummary and PerspectivesReferencesReferences (cntd)Jan M. RabaeyLow Power Design Essentials ©2008Chapter 8Optimizing Power @ StandbyCircuits and SystemsLow Power Design Essentials ©20088.2 Chapter OutlineWhy Sleep Mode Management?Dynamic power in standby–Clock gatingStatic power in standby–Transistor sizing–Power gating–Body biasing–Supply voltage rampingLow Power Design Essentials ©20088.3 Arguments for Sleep Mode ManagementMany computational applications operate in burst modes, interchanging active and non-active modes–General purposes computers, cell phones, interfaces, embedded processors, consumer applications, …Prime concept: Power dissipation in standby should absolutely minimum, if not zeroSleep mode management has gained importance with increasing leakageFixed ActivityVariable ActivityNo Activity - StandbyActiveDesign TimeRun TimeStaticClock gatingLeakageeliminationLow Power Design Essentials ©20088.4 Standby Power - Was Not A Concern In Earlier DaysPentium-1: 15 Watt (5V - 66MHz)Pentium-2: 8 Watt (3.3V- 133 MHz)Floating Point Unit and Cache powered down when not in useProcessor in idle mode![Source: Intel]Low Power Design Essentials ©20088.5 Dynamic Power - Clock GatingTurn off clocks to idle modules–Ensure that spurious activity is set to zeroMust ensure that data inputs to module are in stable mode –Primary inputs are from gated latches or registers–Or, disconnected from interconnect networkCan be done at different levels of system hierarchyLow Power Design Essentials ©20088.6 Clock GatingTurning off the clock for non-active componentsRegister FileRegister FileLogic ModuleLogic ModuleClkEnableLogic ModuleLogic ModuleEnableBusDisconnecting the inputsLow Power Design Essentials ©20088.7 DSP/HIFDEUMIFVDE896Kb SRAM108.5mW015530.6mW20 25Without clock gatingWith clock gatingPower [mW]Clock-gating Efficiently Reduces Power[Ref: M. Ohashi, ISSCC’02]90% of F/F’s clock-gated.70% power reduction by clock-gating alone.MPEG4 decoder© IEEE 2002Low Power Design Essentials ©20088.8 Clock GatingChallenges to skew management and clock distribution (load on clock network varies dynamically)Fortunately state-of-the-art design tools are starting to do a better job–For example, physically aware clock-gating inserts gaters in clock-tree based on timing constraints and physical layoutCGCGCGCGCGSimpler skew management, less areaPower savingsLow Power Design Essentials ©20088.9 Clock Hierarchy and Clock GatingExample: Clock distribution of dual-core Intel Montecito processor“Gaters” provided at lower clock tree levelsAutomatic skew compensation[Ref: T. Fischer, ISSCC’05]© IEEE 2005Low Power Design Essentials ©20088.10 Trade-Off between Sleep-Modes and Sleep-TimeActive modenormal processingStandby modefast resumehigh passive powerTypical operation modes Sleep modeslower resumelow passive powerResume time from clock gating determined by the time it takes to turn on the clock distribution network Standby Options:  Just gate the clock to the module in question Turn off phased-locked loop(s) Turn off clock completelyLow Power Design Essentials ©20088.11 Sleep Modes in mProcessors and mControllers[Ref: S. Gary, Springer’95][Ref: TI’06]• 0.1-μA power down• 0.8-μA standby• 250-μA / MIPS @ 3 VTI MSP430™From standby to active in 1 ms Using dual clock systemLow Power Design Essentials ©20088.12 The Standby Design Exploration SpaceStandby PowerWake-up DelayStandbySleepNapDozeTrade-off between different operational modesShould blend smoothly with run-time optimizationsLow Power Design Essentials ©20088.13 Also the Case for Peripheral Devices[Ref: T. Simunic, Kluwer’02]TX RX Doze OffPower 1.65W 1.4W 0.045W 0 WTransitions To Off:62 msecTo Doze:34 msecWireless LAN CardHard diskPsleepWPactiveWTsleepsecTactivesecIBM 0.75 3.48 0.51 6.97Fujitsu 0.13 0.95 0.67 1.61Low Power Design Essentials ©20088.14 The Leakage Challenge – Power in StandbyWith clock-gating employed in most designs, leakage power has become the dominant standby power sourceWith no activity in module, leakage power should be minimized as well–Remember constant ratio between dynamic and static power …Challenge – how to disable unit most effectively given that no ideal switches are availableLow Power Design Essentials ©20088.15 Standby Static Power Reduction ApproachesTransistor stackingPower gatingBody biasingSupply voltage rampingLow Power Design Essentials ©20088.16 Transistor StackingOff-current reduced in complex gates (see leakage power reduction @ design time)Some input patterns more effective than others in reducing leakageEffective standby power reduction strategy:–Select input pattern that minimizes leakage current of combinational logic module–Force inputs of module to correspond to that pattern during standbyPro’s: Little overhead, fast transitionCon: Limited effectivenessLow Power Design Essentials ©20088.17 Transistor StackingCombinational ModuleLatchesLatches……ClkStandby[Ref: S. Narendra, ISLPED’01]Low Power Design Essentials ©20088.18 Forced Transistor Stacking[Ref: S. Narendra, ISLPED’01]Useful for reducing leakage in non-critical