Slide 1Chapter OutlineRationaleOpportunities for Ultra-Low VoltageMinimum Operational Voltage of InverterSubthreshold Modeling of CMOS InverterSubthreshold DC model of CMOS InverterResults from Analytical ModelConfirmed by simulation (at 90 nm)Also Holds for More Complex GatesMinimum Energy per OperationPropagation Delay of Subthreshold InverterDynamic BehaviorPower Dissipation of Subthreshold InverterPower-Delay Product and Energy-DelayEnergy for a Given ThroughputExample: Energy-Aware FFTFFT Energy-Performance CurvesSubThreshold FFTChallenges in Sub-Threshold DesignLogic Sizing ConsiderationsLogic Sizing ConsiderationsThe Impact of Data DependenciesThe Impact of Data DependenciesThe Sub-Threshold (Low Voltage) Memory ChallengeSolutions to Enable Sub-VTH MemorySub-threshold SRAM CellSub-threshold SRAMExample: Sub-Threshold MicroprocessorPrototype ImplementationIs Sub-threshold the Way to Go?In Addition: Huge Timing VarianceIncreased Sensitivity to VariationsONE SOLUTION: Back Off A Bit …Modeling Over All Regions of InterestRelationship between VDD and ICProvides Good Match over Most of the RangeModeling EnergyHigh Activity ScenarioLow Activity ScenarioExample: AdderOptimizing over size, VDD, VTH (full range)Sensitivity to Parameter VariationsMoving the Minimum Energy PointComplex versus Simple GatesSlide 46Complex versus Simple GatesControlling Leakage in PTLSense-Amplifier Based Pass-Transistor Logic (SAPTL)Sense-Amplifier Based Pass-Transistor Logic (SAPTL)Energy-Delay Trade-offSlide 52ReferencesReferences (cntd)Jan M. RabaeyLow Power Design Essentials ©2008Chapter 11Ultra-Low Power/Voltage DesignLow Power Design Essentials ©200811.2 Chapter OutlineRationaleLower Bounds on Computational EnergySubthreshold LogicModerate Inversion as a Trade-offRevisiting Logic Gate TopologiesSummaryLow Power Design Essentials ©200811.3 RationaleContinued increase of computational density must be combined with decrease in energy/operation (EOP).Further scaling of supply voltage essential to accomplish that–The only other option is to keep on reducing activitySome key questions:–How far can the supply voltage be scaled?–What is the minimum energy per operation that can be obtained theoretically and practically?–What to do about the threshold voltage and leakage?–How to practically design circuits that approach the minimum energy bounds?Low Power Design Essentials ©200811.4 Opportunities for Ultra-Low VoltageNumber of applications emerging that do not need high performance, only extremely low power dissipationExamples:–Standby operation for mobile components–Implanted electronics and artificial senses–Smart objects, fabrics and e-textilesNeed power levels below 1 mW (even mW in certain cases)Low Power Design Essentials ©200811.5 Minimum Operational Voltage of InverterSwanson, Meindl (April 1972)Further extended in Meindl (Oct 2000)Limitation: gain at midpoint > -1Cox: gate capacitanceCd: diffusion capacitancen: slope factorFor ideal MOSFET (60 mV/decade slope):)1ln()(2(min))2ln()(2(min)nqkTVCCqkTVDDoxdDDVqkTqkTVDD036.038.1)2ln(2(min) at 300° Kor[Ref: R. Swanson, JSSC’72; J. Meindl, JSSC’00]© IEEE 1972Low Power Design Essentials ©200811.6 Subthreshold Modeling of CMOS InverterFrom Chapter 2:qkTVqkTnVqkTVqkTnVVSDSDSGSDSTHGSeeIeeII 110(DIBL can be ignored at low voltages)withqkTnVSTHeII0Low Power Design Essentials ©200811.7 Subthreshold DC model of CMOS InverterAssume NMOS and PMOS are fully symmetrical and all voltages normalized to the thermal voltage FT = kT/q(xi = Vi/FT; xo = Vo/FT; xD = VDD/FT)The VTC of the inverter for NMOS and PMOS in subthreshold can be derived:[Ref: E. Vittoz, CRC’05])24)1(1ln(2DxDoGeGGxxwithnxxDieG/)2( so that)2()1(2oDoDDoDoxxxxxxxxVeeeneeeAneADxV/)1(2/maxandFor |AVmax| = 1: xD = 2ln(n+1)Low Power Design Essentials ©200811.8 Results from Analytical Model1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 21234567nxdAmax=1Amax=2Amax=4Amax=10Normalized VTC for n=1.5 as a function of VDD (xd)Subthreshold InverterMinimum supply voltage for a given maximum gain as a function of the slope factor n[Ref: E. Vittoz, CRC’05]xdmin = 2ln(2.5) = 1.83 for n=1.5xd =4 sufficient for reliable operationxD=8xD=6xD=4xD=1xD=2n=1.50 1 2 3 4 5 6 7 8012345678xixoLow Power Design Essentials ©200811.9 Confirmed by simulation (at 90 nm)0.5 1 1.5 2 2.5 34045505560657075808590Observe: non-symmetry of VTC increases V DDminFor n =1.5,VDDmin = 1.83 FT= 48 mVMinimum operational supply voltagepn-ratioVDDmin (mV)Low Power Design Essentials ©200811.10 Also Holds for More Complex GatesDegradation due toasymmetryMinimum operational supply voltage(2-input NOR)pn-ratioLow Power Design Essentials ©200811.11 Minimum Energy per OperationMoving one electron over VDDmin:–Emin = QVDD/2 = q 2(ln2)kT/2q = kTln(2)–Also called the Von Neumann-Landauer-Shannon bound–At room temperature (300K): Emin = 0.29 10-20 J Minimum sized CMOS inverter at 90 nm operating at 1V–E = CVDD2 = 0.8 10-15 J, or 5 orders of magnitude larger!J. von Neumann,[Theory of Self-Reproducing Automata, 1966].Predicted by von Neumann: kTln(2)How close can one get?[Ref: J. Von Neumann, Ill’66]Low Power Design Essentials ©200811.12 Propagation Delay of Subthreshold InverterTDDnVDDonDDpeICVICVt0Normalizing tp to t0 = CFT/I0:nxDppDext/0(for VDD >> FT)Comparison betweencurve-fitted model and simulations (FO4, 90 nm)3 4 5 6 7 8 9 10020406080100120xdtpt0 = 338n = 1.36(nsec)Low Power Design Essentials ©200811.13 Dynamic BehaviorAlso: Short circuit current ignorable if input rise time smaller than t0, or balanced slopes at in- and outputs0 0.5 1 1.5 2 2.500.10.20.30.40.50.60.70.80.91Time (normalized to t0)Voltage (norm. to 4FT)Transient responsetr = 2t0t00.5t00tptp as a function of trise0 0.5 1 1.5 2 2.5 30.10.150.20.250.30.350.40.450.5trisetp(normalized to t0)xD = 4Low Power Design Essentials ©200811.14 Power Dissipation of Subthreshold InverterPdyn = CVDD2f (nothing new)Short-circuit power can be ignored (< 1%) for well-proportioned circuits and xD >= 41 2 3 4 5 6 7 8 9 100.50.60.70.80.911.11.21.3xDIStatI0n=1.5circuit failslogic levels degenerateLeakage current equal to I0 for xD >= 4 (ignores DIBL)Increases for smaller values of xD due to degeneration of logic