On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design GoalsIntroductionOur workEvaluation Approach and ModelsSlide 5Slide 6Minimum DelayExperimental results: wire configurationSlide 9Experimental results: metric evaluationSlide 11On-Chip Interconnect Analysis and On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Evaluation of Delay, Power, and Bandwidth Metrics under Different Bandwidth Metrics under Different Design GoalsDesign GoalsIntroduction•Interconnect strategy, or interconnect planning has become a critical part of chip design:•the growing significance of wire delay relative to gate delay .•increasing power consumption of wires: could be up to 50% of the total dynamic power.•Influences the ASIC design methodologyOur work•Try to revamp the on-chip local interconnect configuration for multi-objective optimization:–Compare different objective functions.–Formulate various matrics to measure the wire performance.–Identify the optimal wire configurations.Evaluation Approach and Models•objective functions:– is the wire-length normalized delay.– is the wire-length-normalized power.ndelayn ndelay power�2n ndelay power�ndelaynpowerEvaluation Approach and Models•Metrics–is amount of data that can be transferred per unit area per unit time.ndelaynpowerbandwidth/bandwidth powerEvaluation Approach and Models•Models–Elmore delay model:–Power model:–Leakage factor:0 0(1 )(1 )(1 )stagenmos wn w w inv w nmos invinv inv invdb g f r c br cdelay ar c l b g r c sl l s+ += = + + + +2(1.1 )(1 )(1 )stageleak nmos invn w ddinv invpf g c spower c vl lh� �+ + += = +� �� �Minimum Delay•Optimum repeater interval and size:•Optimum delay and powerExperimental results: wire configuration0 0.2 0.4 0.6 0.8 1 1.2x 10-6020406080100120140min-dmin-ddpmin-dppitch(m)inverter size180nm130nm100nm70nm0 0.2 0.4 0.6 0.8 1 1.2x 10-60123456789x 10-7min-dmin-ddpmin-dppitch(m)width(m)180nm130nm100nm70nmOptimal inverter sizesOptimal widths0 0.2 0.4 0.6 0.8 1 1.2x 10-600.511.522.5x 10-3pitch(m)inverter distance(m)180nm130nm100nm70nm0 0.2 0.4 0.6 0.8 1 1.2x 10-600.511.522.53x 10-3pitch(m)inverter distance(m)180nm130nm100nm70nm0 0.2 0.4 0.6 0.8 1 1.2x 10-600.511.522.53x 10-3pitch(m)inverter distance(m)180nm130nm100nm70nmOptimal inverter distances in the min-dp procedureOptimal inverter distances in the min-ddp procedureOptimal inverter distances in the min-d procedureExperimental results: metric evaluation5010015020000.511.5x 10-600.511.52x 10-7delayn(s/m)min-dmin-ddpmin-dp50100150200012x 10-60123456x 10-10power(J/m)min-dmin-ddpmin-dpndelaynpower5010015020000.511.5x 10-612345x 1013bandwidth(bits/s)min-dmin-ddpmin-dp5010015020000.511.5x 10-6012345x 1023bandwidth/power(m/Js)min-dmin-ddpmin-dpExperimental results: metric evaluationbandwidth/bandwidth