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UCSD CSE 241A - Low Power SOC Design and Automation

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Matt SeversonQualcomm CDMA TechnologiesJuly 27, 2009Low Power SOC Design and Automation Introduction  Overview of Serra (Qualcomm’s first 45nm tapeout) Features / Technology / Low Power Techniques Tradeoffs of Automated vs. Custom Design for Low Power Memory IP Standard Cell  Mixed-Vt Design Clock Power Clock Gating Clock Tree Synthesis Multiple Power Domains Voltage Scaling Voltage Islands with Power Gating Conclusions & Future DirectionsOutline2July 2009Introduction Power consumption is a key differentiator in wireless communications products. Power Consumption Limits Battery Life Performance  Feature set  Form Factor 3July 2009Introduction – Form FactorJuly 2009 4Phone Surface Temperature Rise Above AmbientSurface Power Density [W/sq-in]0.02 0.03 0.05 0.07 0.2 0.3 0.5 0.80.01 0.1 1Temperature Rise, [C]235720305080110100Surface Power Densities less than 0.1 W/sq-inThis is the recommended design areaSurface Power Densities between 0.1 and 0.22W/sq-inPhone is likely to have local hot spotsSurface Power Densities greater than 0.22W/sq-inPhone should be redesigned Power Densities Increasing Overheating Limit Form FactorsIntroduction - Battery Life5July 200944%43%21%28%14%26%35%12%19%48%0%20%40%60%80%100%Device 1Device 2Device 3Device 4Device 5Device 6Device 7Device 8Device 9Device 10% of Total ReviewsBattery Life Analysis1 Star (Bad)2 Stars3 Stars4 Stars5 Stars (Good)Expressed DissatisfactionVerizon™A T & T™Battery CapacityScreen Pixels860 mAh 800 mAh 800 mAh 1400 mAh240 x 320 240 x 320 240 x 320 360 x 480930 mAh 1300 mAh 1130 mAh 1500 mAh 910 mAh 880 mAh240 x 320 240 x 400 240 x 320 240 x 320 240 x 320 176 x 220PhoneChipsetSERRAQualcomm’s First 45nm TapeoutJuly 2009 6Serra Feature SetJuly 2009 7 Modemo CDMA 1xEV-DO revA & Bo UMTS (includes HSDPA, HSUPA)o GSM (includes GPRS and EDGE)o Unified GPS engine for both CDMA and UMTS modes.  Processorso QDSP4u8 based MDSP core o ARM11 core with 32KB I/D cacheo ARM926 core with 32KB I/D cache o QDSP5u4 based ADSP core w/ 256 KB L2 cache Multimediao 24 bit WVGA w/ LCDC (active refresh)o ATI LT graphics core (Open GL 2.0)o 22M Triangles/Seco 8 Mpixel Camera support Peripherals 2 HS USB interfaces o MDDI gen 1.5Serra Physical CharacteristicsDie size: 8200.08 x 6500.34 um (53.3 mm^2)Signal I/Os: 419Process: tsmc45lpMetal Layers: 6 (5 thin, 1 thick (4x)) and 1 AP RDL layerTotal # Transistors: 170 MillionTotal # RAM bits: 13.7 Mbits Total # ROM bits: 1.1 MbitsStatic IR Drop: < 10mV (@ Worst case 800 mA)Leakage: ~450 uA (TT,25c, 1.125V)671 pin 13x13 NSP Package 0.5mm ball pitchIncludes Serra (Digital die) + Analog + Memory8July 2009Serra Low Power Design Goals Background Leakage Power is increasing due to process 45nm Sub-Threshold is worse than 65nm (pA/um) Gate leakage is increasing. Junction Diode leakage is increasing. 45nm Process has no HVt transistor. Simple scaling of Dynamic Power is not Enough.  + Dynamic Power will scale down with process geometries (-C)(-V)o However increased wire cap will temper the reduction - Increased performance demands and more applications (+f) (+C) - Aggressive Product requirements for battery life Conclusion:  More aggressive leakage and active power management techniques are required in 45nm Low Power Priorities / Goals for Serra: 1 Decrease Dynamic Power 2 Maintain the total static leakage power.  3 Keep Active Leakage a “small” percentage of Dynamic Power (< ~15%)9July 2009Serra Low Power Features Low Power Multi-Threshold Qualcomm Standard Cell Libraryo 2 Vt and 2 Channel Lengths Low Power Memoryo Power Collapsing of RAM/ROM periphery and coreo Independent Bank Collapsing for Large High Density Memories Advanced Low Power Clockingo ~105 Master Clock Domains (I/O or Independent Frequency)o ~230 Total Clock Domains (Synchronous, Iso-Synchronous, Asynchronous)o Automatically inserted Fine grained clock gatingo Manually inserted Architectural clock gateso Static SW control and Dynamic HW control of clock gating.o Custom Raw Clock Tree Routingo Low Power CTS with Qualcomm Custom Clock Tree cells.  24 Analog and Pad power domains 2 Digital Power domainso Independent Voltage Scaling– Active and Sleep modeso Power Collapsing 8 Digital Power Islands with Power Gating All Low Power Features fully Verified Power Aware simulation Power Structural Checks10July 2009Serra Floorplan11July 2009Serra Static IR Drop Map12July 2009Serra Dynamic IR drop Map13July 2009DESIGN AUTOMATION Design Automation is Mandatory Design complexity  Time to Market is Critical Fewer design resources required Qualityo Through Standardized flows and tools Automated Design tools and flows have several limitations that affect low power Many automated tools don’t consider power Others don’t make the correct tradeoffs between power and area/timing. This Presentation focuses on the tradeoffs involved with several low power techniques used on Serra and the limitations of automated design for low power July 200915Design AutomationCustomized Design for Low Power Custom design flows and circuits can produce better results Lower Power, Higher Speeds, Less Area Custom design requires more design effort and time Use customized Design and signoff ONLY in critical areas Pick areas of customization to get the greatest benefit  Clock Trees Raw Clock Trees Raw Clock Dividers Memory IP Standard Cell o Move the customization into IPo Use automation to insert the IP, check the IP and optimize with IP.16July 2009Customization of Raw Clock Network Raw clock networks are high speed, high power nets from PLLs to dividers Raw clock dividers are stacked and custom routed. Width and spacing are chosen for optimal clock isolation while maintaining fast transition times.  Use minimal clock buffers to distribute clocks within the network but maintain desired transition delay. 10-input tri-state mux Reduces insertion delay and power Custom Layout of raw dividers Reduces critical path delay, voltage noise and optimizes rise/fall times. ~4x reduction in Raw clock Power (Compared to Previous chip)Selected Clock Path (green)Non-Selected Active Clocks (red)Traditional Wide Mux StructurePLL PLLPLLPLLRaw Clock Network17July 2009LOW POWER IPPeripheralwith footerBit-cell array with


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UCSD CSE 241A - Low Power SOC Design and Automation

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