ECE260B – CSE241A Winter 2010 Low power implementation A system perspectiveLow power implementation : MetricsLow power implementation : MetricsLow power implementation: Design synergy System optimization Architectural optimizationArchitectural optimizationArchitectural optimizationLow power techniques: Power gatingLow power techniques: Power gatingLow power techniques: Power gatingLow power techniques: Power gatingLow power techniques: Power gatingLow power techniques: Clock gatingLow power techniques: Clock gatingLow power techniques: Clock gatingLow power techniques: Clock gatingLow power techniques: AVSLow power techniques: DCVSLow power techniques: SVSBuilding blocks optimization (IP’s)Building blocks optimization: Standard cellsBuilding blocks optimization: Standard cellsBuilding blocks optimization: Standard cellsBuilding blocks optimization: Standard cellsBuilding blocks optimization: Standard cellsBuilding blocks optimization: Standard cellsBuilding blocks optimization: MemoriesBuilding blocks optimization: MemoriesPhysical design optimizationPower verificationECE240B/CSE241A Low power techniques 1 Sorin Dobre, QualcommECE260B – CSE241AWinter 2010Low power implementationA system perspectiveWebsite: http://cseweb.ucsd.edu/classes/wi10/cse241a/ECE240B/CSE241A Low power techniques 2 Sorin Dobre, QualcommLow power implementation : Metrics User experience prospective: For mobile devices: - Active time of the device: Time interval of performing a well defined set of tasks (defined use mode: audio play , voice call, web browsing, video playback, etc ) between two battery charges- Standby time of the device: Time interval between two battery charges when the device is fully functional ready to be activated but does not perform any functional user driven tasks. For electrical powered devices: Efficiency: Power consumption for performing a defined set of tasks relative to performance metrics:- mW/Mhz Average power consumption Peak power consumptionECE240B/CSE241A Low power techniques 3 Sorin Dobre, QualcommLow power implementation : Metrics Power consumption in digital systems: Ptotal = Pactive + PleakagePactive = Pinternal + Pswitching = Pinternal + αCV²fV – voltagef – frequencyC – capacitive loadα – activity factorECE240B/CSE241A Low power techniques 4 Sorin Dobre, QualcommLow power implementation: Design synergy Low power implementation in the modern system on chips today requires a holistic and concurrent approach which includes collaboration between: System level design Architectural design Software Hardware co-design IP design:- Circuit design- Physical implementation of the IP Physical design (chip/block level) Power verification and modeling Silicon correlation and validationECE240B/CSE241A Low power techniques 5 Sorin Dobre, QualcommSystem optimization  Power delivery network optimization: On die vs on board (PCB) voltage regulators Voltage regulators efficiency Voltage rails definition  System level power management:- Adaptive voltage scaling (AVS)- Dynamic clock frequency and voltage scaling (DCVS)- Static voltage scaling (SVS) Analog vs digital processing system level optimization Optimization at the system with the goal of moving most of the signal processing (data transformation) in the digital domain. The power consumption in the digital domain is scalable with the process technology scaling and with the system use mode requirements.  Digitally assisted analog processingECE240B/CSE241A Low power techniques 6 Sorin Dobre, QualcommArchitectural optimization Memory hierarchy On die vs. off die memory Cache size (miss penalty) Cache hierarchy (architecture) Address space definition  Processor architecture Von Neumann , Harvard VLIW (high IPC) 16bit, 32bit, 64 bit instruction architecture (IA) (Code compression) In order vs out of order execution Superscalar implementation Multi thread implementation  Scalability : Single core vs. Multi core Application specific IA optimization- FFT cores-Multipliers, adders ,shiftersECE240B/CSE241A Low power techniques 7 Sorin Dobre, QualcommArchitectural optimization Hardware accelerators: Graphic 2D, 3D Video encoder/decoder (720p, 1080p) Multimedia display Audio + DSP (digital signal processing unit)  Modem baseband Bus architecture AHB implementation (Advanced high performance bus)  AXI  Fabric (high speed, high bandwidth interconnect):- Bandwidth- Latency - Power Clocking architecture: PLL’s Frequency planning Clock architecture Synchronous vs asynchronous clocksECE240B/CSE241A Low power techniques 8 Sorin Dobre, QualcommArchitectural optimization IO interfaces  DDR (LPDDR), SDIO PCI-X, USB, MIPI, HDMI, GPIO  Engineering system level design and optimization (ESL): Algorithmic driven hardware implementation and optimization System level power modeling Hardware software co-design and optimizationECE240B/CSE241A Low power techniques 9 Sorin Dobre, QualcommLow power techniques: Power gating Widely use in all the portable devices today: Global distributed foot-switch GDFS Global distributed head-switch GDHS Main goal to eliminate the current leakage (reduce leakage power) in standby mode.ENVddxGND(vssx)Virtual GND (vssfx)GDFS blockLeakage currentIleakln=60nmInterface blockx Leakage savings. (+) Voltage droop (-)  Area overhead. (-) Routing resources (-) Leakage savings mode : High Roff (~ GΩ) Functional mode : Low Ron Isolation cells required for the output signals of the block in sleep mode to avoid undefined logic state propagation 10X to 1000X leakage savingECE240B/CSE241A Low power techniques 10 Sorin Dobre, QualcommLow power techniques: Power gating Chanel length modulation:ECE240B/CSE241A Low power techniques 11 Sorin Dobre, QualcommLow power techniques: Power gatingFS RingGlobal PG Mesh Local PG Mesh vvvvvvvvvvvvvvvvvvGDFS  Global distributed FS/HS Can be modeled as an additional resistance between global and local power mesh Does not break global mesh Needs sleep control signal distribution Suitable for large size macros FS/HS ring Smaller cost on sleep control distribution Larger IR drop compared with GDFS, especially for flip-chip case  IR drop increases quicker when the size of the block increases (cubic w.r.t. the length)