UCSD CSE 241A - Adaptive Circuits (33 pages)

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Adaptive Circuits



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Adaptive Circuits

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Pages:
33
School:
University of California, San Diego
Course:
Cse 241a -
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ISSCC2009 Keynote Adaptive Circuits for the 0 5 V Nanoscale CMOS Era Kiyoo Itoh Hitachi Ltd Tokyo Japan 2009 IEEE International Solid State Circuits Conference 2009 IEEE OUTLINE 1 Introduction The 1 V wall 2 Adaptive Circuits for Memory Rich LSIs Trends in Vmin Breakthrough technologies Scenario to the 0 5 V nanoscale era 3 Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4 Conclusion K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE VDD Vmin V The 1 V Wall 5 4 3 MPUs ISSCC Vmin Min op VDD VDD Power crisis 2 1 0 8 0 6 Vmin RDF 0 4 0 2 800 350 180 90 Target 45 22 11 Device feature size F nm RDF Random Dopant Fluctuation K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE What should we do to lower VDD 1 Reduce min operating VDD Vmin by reducing Lowest necessary Vt Vt0 Intrinsic Vt variation Vt New devices circuits repair etc 2 Reduce power supply noise Vps Compact subsystems small core chip 3 D chip stack etc Reducing Vmin is the key Vmin Vps K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE OUTLINE 1 Introduction The 1 V wall 2 Adaptive Circuits for Memory Rich LSIs Trends in Vmin Breakthrough technologies Scenario to the 0 5 V nanoscale era 3 Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4 Conclusion K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Circuits Giving Low VDD Limitations Most sensitive to Vt Chip Logic block Inverter SRAM Cell DRAM SA RAM block Peri Array WL cell DL DL Vt LW Count large 8F 2 av large largest 1 5 3F 2 largest small 15F 2 medium Vt 1 LW F device feature size K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Definition of Vmin Inverter SRAM Cell VDD VDD DL DRAM SA SP 0 DL DL DL VDD vS SN Vt VDD VDD Vt 1 2 Vmin VDD for a fixed Vt0 1 Vtmax Vt0 Vtmax Vt0 VDD Vt0 VDD Vt0 Vtmax 1 2 1 1 1 2 1 Tolerable speed Vt0 Lowest necessary av Vt variation VTmax Max variation in Vt 2 3 for 1 4 1 6 K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE High and Unscalable Vt0 Subthreshold leakage A HP high performance LP low power 102 101 100 10 1 10 2 10 3 Vt0 ext Vt0 nA m 0 3 V Tj 75 C 130 nm 1 Mb SRAM LP 64 K DRAM SAs 10 4 10 5 10 6 10 7 HP 10 8 0 2 K Itoh 1 Mgate Logic HP 0 0 2 LP 0 4 0 6 Vt0 ext 25 C 0 8 1 contributing to leakage in active standby mode 2009 IEEE International Solid State Circuits Conference 2009 IEEE Vtmax 10 m circuit count Avt LW tox Vt0 0 1 V 0 5 Nsub0 25 For lower Vtmax use 1 Repair ECC Redundancy m 1 2 2 Small technologies Avt mV m tOX nm Vtmax m Circuits tolerating The largest MOSFET possible The lowest Vt0 possible Small Avt MOSFETs K Itoh et al p 68 ESSCIRC2007 K Itoh 2009 IEEE International Solid State Circuits Conference 5 4 3 2 Conv tOX High k MG tOX FD SOI Nsub 4 2 Avt tOX 2 5 1 5 1 0 5 0 4 0 3 FD SOI EOT 0 5 nm 250 180 130 90 65 45 32 Device feature size F nm K Takeuchi et al p 467 IEDM 2007 2009 IEEE ECC Redundancy W ECC Words Redundant Words 6 parity bits SRAM DRAM 6 0 r 0 5 5 5 data bits defective cell 0 001 m N 4 0 01 3 0 1 SRAM 0 4 DRAM 3 3 2 9 1 replace 2 ECC word with one defect SRAM b 32M 64M 128M 256M DRAM b 128M 256M 512M 1G cell corrected by ECC ECC word with two or more defect replaced by a redundant word K Itoh r repairable Max r 0 1 SRAMs 0 4 DRAMs 2009 IEEE International Solid State Circuits Conference K Itoh ESSCIRC2007 Dig pp 68 75 2009 IEEE Trends in Vmin 1 0 Vt 4 2 Logic SRAM 0 Repair for RAMs 4 0 V Logic SRAM V Vmin V 2 V V Repair for RAMs 0 3 Avt LW LW 8F 2 L 1 5F 2 SRAM 15F 2 DRAM Avt 4 2 mV m Conv Avt 1 5 mV m Hi k MG SOI 0 2 K Itoh V 2 V 0 4 V 0 2 DRAM V DRAM F nm 250180 130 90 65 45 32 22 15 11 Logic g SRAM b DRAM b 0 0 2 0 5 0 4 V t0 4 0 250 180 130 90 65 45 32 22 15 11 1 3M 5M 20M 80M 320M 1 3M 5M 20M 80M 320M 8M 32M 128M 512M 2G 8M 32M 128M 512M 2G 32M 128M 512M 2G 32M 128M 512M 2G 8G 8G 2009 IEEE International Solid State Circuits Conference 2009 IEEE State of the Art SRAM Cells Increased cell power supply VDD VDL Dynamic S control VDD 0 VDL 0 STB ACT 0 Dynamic S control VDL or float W 8 T cell RWL WWL 0 VDD M2 M1 WDL WDL RDL K Itoh p 132 VLSI Circuits 96 H Akamatsu p 14 VLSI Circuits 96 F Hamzaoglu ISSCC 08 p 376 L Chang p 252 VLSI Circuits 96 K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Reduction in Vmin of SRAMs Vmin V 2 1 6 repair Avt 2 5 mV m 1 LW F 2 1 0 5 0 4 0 3 6 T cell vs 8 T cell 0 0 4 V Vt 2 0 V LW F W fixed W fixed Cell size ratio 3 6 T cell 0 5 0 4 0 3 8 T LW F 2 156 185F 2 LW F 2 120F 2 LW F W fixed at 90 nm 0 2 at at90 90nm nm 0 2 F nm 250 130 65 32 15 SRAM b 4M 16M 64M 256M 1G K Itoh 6 T 2009 IEEE International Solid State Circuits Conference 0 1 130 90 65 45 32 22 15 11 Device feature size F nm 2009 IEEE Breakthrough Technologies for reducing Vmin and Vps The best way to predict the future is to invent it Vmin Vt0 1 m Vt0 0 1 V 0 5 1 2 a u 1 Adaptive devices circuits Vmin scalable FinFET Dual VDD dual Vt0 circuit 2 Adaptive tech Vps with small chip compact subsystem 2 D selection FinFET cell Many core and chip stack 1 0 0 8 0 6 0 4 0 2 0 0 1 0 2 0 3 0 4 0 5 0 6 Vt0 V Future Perspectives ISLPED 02 August 2002 K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Assumptions for Avt and Vt0 Avt LW 1 device scaling factor Avt mV m tOX nm 10 5 4 3 2 Poly Si …


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