Adaptive Circuitsfor the 0.5-V Nanoscale CMOS Era Kiyoo ItohHitachi Ltd., Tokyo, JapanISSCC2009 Keynote© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohOUTLINE1. IntroductionThe 1-V wall2. Adaptive Circuits for Memory-Rich LSIsTrends in VminBreakthrough technologiesScenario to the 0.5-V nanoscale era3. Adaptive Circuits for Mixed Signal LSIsDigital assisted analog design4. Conclusion© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohThe 1-V WallDevice feature size, F (nm)80035090452211VDD Target180Vmin(RDF)543210.4VDD, Vmin(V)0.20.60.8MPUs(ISSCC),Vmin: Min. op. VDDPower crisisRDF: Random Dopant Fluctuation© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohWhat should we do to lower VDD?1. Reduce min. operatingVDD(Vmin) by reducing •Lowest necessary Vt(Vt0), •Intrinsic Vt-variation (ΔVt).→ New devices, circuits, repair etc.2. Reduce power-supply noise (Vps)→ Compact subsystems (small core/chip,3-D chip stack) etc. Reducing Vminis the key. (Vmin»Vps) © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohOUTLINE1. IntroductionThe 1-V wall2. Adaptive Circuits for Memory-Rich LSIsTrends in VminBreakthrough technologiesScenario to the 0.5-V nanoscale era3. Adaptive Circuits for Mixed Signal LSIsDigital assisted analog design4. Conclusion© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohCircuits Giving Low-VDDLimitations * Most sensitive to ΔVtΔVtlarge largest smallLW 8F 2(av.) 1.5-3F 215F 2Count large largest medium Inverter SRAM Cell* DRAM SA*ΔVt∝ 1/√LW, F : device feature sizeChipLogic blockRAM blockPeri. ArrayDLcellWLDL© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohDefinition of Vminτ(Vt) ∝VDD/(VDD –Vt)1.2Δτ=τ(Vt0+ ΔVtmax)/τ(Vt0)={(VDD –Vt0)/(VDD –Vt0 –ΔVtmax)}1.2Vt0 : Lowest necessary av.VtΔVTmax:Max. variation in VtVmin=VDDfor a fixed Δτ=Vt0+ (1 +γ) ΔVtmaxγ= 1/(Δτ1/1.2 –1)Δτ: Tolerable speed variation γ≅ 2–3 for Δτ=1.4 –1.6Inverter SRAM Cell DRAM SAVDDDLDL0SPVDD -vSDLSNDLVDD© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohHigh and UnscalableVt0 Subthreshold leakage (A)10-810-710-610-510-410-310-210-1100101102-0.200.2 0.4 0.61Tj= 75°C, 130 nmVt0(ext, 25°C)Vt0 (ext) =Vt0 (nA/μm) + 0.3 V1-Mgate Logic1-Mb SRAM64-K DRAM SAs*0.8HP LPHPLP* contributing to leakage in active standby modeHP: high performance, LP: low power© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohΔVtmaxK. Itoh et al., p. 68, ESSCIRC2007 K. Takeuchi et al., p. 467, IEDM 2007ΔVtmax= mσ•m → circuit count •σ= Avt/√LW ∝{tox(Vt0 + 0.1 V)}0.5 ∝Nsub0.25 For lower ΔVtmax, use1. RepairECC + Redundancy (m->1/2)2. Small σtechnologies•Circuits tolerating The largest MOSFET possibleThe lowest Vt0possible•Small-AvtMOSFETsAvt(mVμm), tOX(nm)Device feature size, F (nm)10543210.50.40.3Avt2.51.5FD-SOI, EOT = 0.5 nmtOX250 130906545321804.2Conv. (tOX↓)High-k MG (tOX↓)FD-SOI (Nsub↓)© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohECC + RedundancyRedundant Words•ECC word with one defect cell corrected by ECC.•ECC word with two or more defect replacedby a redundant word. parity bitsdatabitsNWECC Wordsdefective cellreplaceK. Itoh, ESSCIRC2007 Dig., pp. 68-75r : repairable % Max r = 0.1%(SRAMs), 0.4%(DRAMs). 32M 64M 128M 256MSRAM(b)128M 256M 512M 1GDRAM(b)m3.32.92460.1 (SRAM)0.010.001%r= 0%SRAM DRAM5.56.00.4 (DRAM)153© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohTrends inVminσ= Avt/√LWLW= 8F 2(L), 1.5F 2(SRAM), 15F 2(DRAM)Avt= 1.5 mVμm(Hi-k MG, SOI)Avt= 4.2 mVμm(Conv.)F(nm)Logic (g)0.2 V0.4 V0.2 VVt0= 0.4 VVmin(V)0.2210.50.43SRAM (b)DRAM (b)8G130652501809045 32 22 151132M1.3M5M20M 80M320M8M32M128M 512M2G128M512M2GRepair for RAMsDRAMLogicSRAM8G320MRepair for RAMsVt0= 0.4 V0.2 V0.4 V0.2 VDRAMLogicSRAM130652501809045 32 22 151132M1.3M5M20M 80M8M32M128M 512M2G128M512M2G© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohDynamic S-control 8-T cellState-of-the-Art SRAM CellsWDLVDDWWLRWLRDLWDLM1M2VDL or float (W)VDD (>VDL)0VDLVDDSTB ACT000Increased cell-power supply Dynamic S-control K. Itoh, p. 132, VLSI Circuits’96; H. Akamatsu, p. 14, VLSI Circuits’96; F. Hamzaoglu, ISSCC’08, p. 376; L. Chang, p. 252, VLSI Circuits’96 © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohReduction in Vminof SRAMs6-T cell 6-T cell vs 8-T cell8-T, LW ∝F 2156-185F 2LW ∝F 2120F 26-TLW ∝F Wfixed at 90 nm11Cell size (ratio)10.50.40.30.20.113090 65 4532 2215Device feature size, F (nm)LW ∝F Wfixed at 90 nmVt0= 0.4 V0.2 VLW∝F 2SRAM(b)6532130 1525064M 256M16M1GΔτ= 1.6, repairAvt= 2.5 mVμmF(nm)30.2210.50.40.3Vmin(V)4MLW ∝F Wfixed at 90 nm© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEEK. ItohBreakthrough Technologies1. Adaptive devices/circuits(Vmin↓)•σ-scalable FinFET•Dual-VDDdual-Vt0circuit2. Adaptive tech. (Vps↓) with small chip/compact subsystem • 2-D selection FinFET cell •