UCSD CSE 241A - Adaptive Circuits (33 pages)

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Adaptive Circuits



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Adaptive Circuits

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Pages:
33
School:
University of California, San Diego
Course:
Cse 241a -

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ISSCC2009 Keynote Adaptive Circuits for the 0 5 V Nanoscale CMOS Era Kiyoo Itoh Hitachi Ltd Tokyo Japan 2009 IEEE International Solid State Circuits Conference 2009 IEEE OUTLINE 1 Introduction The 1 V wall 2 Adaptive Circuits for Memory Rich LSIs Trends in Vmin Breakthrough technologies Scenario to the 0 5 V nanoscale era 3 Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4 Conclusion K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE VDD Vmin V The 1 V Wall 5 4 3 MPUs ISSCC Vmin Min op VDD VDD Power crisis 2 1 0 8 0 6 Vmin RDF 0 4 0 2 800 350 180 90 Target 45 22 11 Device feature size F nm RDF Random Dopant Fluctuation K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE What should we do to lower VDD 1 Reduce min operating VDD Vmin by reducing Lowest necessary Vt Vt0 Intrinsic Vt variation Vt New devices circuits repair etc 2 Reduce power supply noise Vps Compact subsystems small core chip 3 D chip stack etc Reducing Vmin is the key Vmin Vps K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE OUTLINE 1 Introduction The 1 V wall 2 Adaptive Circuits for Memory Rich LSIs Trends in Vmin Breakthrough technologies Scenario to the 0 5 V nanoscale era 3 Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4 Conclusion K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Circuits Giving Low VDD Limitations Most sensitive to Vt Chip Logic block Inverter SRAM Cell DRAM SA RAM block Peri Array WL cell DL DL Vt LW Count large 8F 2 av large largest 1 5 3F 2 largest small 15F 2 medium Vt 1 LW F device feature size K Itoh 2009 IEEE International Solid State Circuits Conference 2009 IEEE Definition of Vmin Inverter SRAM Cell VDD VDD DL DRAM SA SP 0 DL DL DL VDD vS SN Vt VDD VDD Vt 1 2 Vmin VDD for a fixed Vt0 1 Vtmax Vt0 Vtmax Vt0 VDD Vt0 VDD Vt0 Vtmax 1 2 1 1 1 2 1 Tolerable speed Vt0 Lowest necessary av Vt variation VTmax Max variation in Vt 2 3 for 1 4 1 6



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