Level Conversion for Dual-Supply Systems Fuji0 Ish i ha ra' ,* Farhana Sheikh' Borivoje Nikolic' 'Department of EECS, University of California, Berkeley, USA Broadband System LSI Project, System LSI Division, Toshiba Corporation, Japan {fuji, farhana, bora}@eecs.berkeley.edu 2 ABSTRACT Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Novel flip-flops presented in this paper incorporate a half-latch LC and a precharged LC. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip- flop. These benefits are accompanied by 24% robustness improvement and 18% layout area reduction. Categories and Subject Descriptors General Terms Keywords B.6.1 [Design Styles]: Sequential circuits - design styles. Design, Performance. Level conversion, dual-supply voltage, flip-flop. 1. INTRODUCTION Power dissipation is a limiting factor in both high-performance and mobile applications. Independent of application, desired performance is achieved by maximizing operating frequency under power constraints that may be dictated by battery life, chip packaging andor cooling costs. Lowering supply voltage results in a quadratic reduction in power dissipation but significantly impacts delay. In constant-throughput applications, this performance loss is recovered by increased pipelining or parallelism [ 11, but it increases the latency of the design. A multiple supply voltage design in which a reduction in supply voltage is applied only to circuits outside critical paths can save power without sacrificing either throughput or latency. A key challenge in designing efficient multiple-supply circuits involves minimizing the cost of level converters (LC) placed on the boundary between 1ow-V~~ (VDDL) and high-VDD (VDDH). A level converter restores a VDDH swing from a VDDL signal in order to prevent DC current due to incomplete PMOS cut-off. A PMOS cross-coupled LC [ 121 is widely used to suppress the DC current. While cost-minimized level conversion has been proposed for a custom data-path design [SI, an effective solution for synthesized Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED '03, August 25-27, 2003, Seoul, Korea. Copyright 2003 ACM 1-581 13-682-X'03/0008. ..$5.00. ASICs is necessary. Dual-supply voltage (dual- VDD) design using a clustered voltage scaling (CVS) scheme proposed in [ll] combines a level converter with a flip-flop in order to minimize area and delay penalties, but very few level-converting flip-flop (LCFF) structures have been investigated [3,5]. In this paper, we present several new LCFF circuits which exhibit improved energy-delay product values and reduced system-level power without incurring robustness degradation or significant area increase over a conventional flip-flop. 2. DUAL-SUPPLY DESIGN 2.1 Optimal VDDL Selection A theoretical model to investigate power reduction via CVS is proposed in [3]. We employ this top-down approach to determine the VDDL/VDDH ratio for LCFF optimization and comparisons. By using parameters for 0.13pm technology, the optimal VDDL is found to sit between 60% and 70% of VDDH regardless of path delay distribution shapes. The latter value is chosen for higher noise immunity of VDDL signals against VDDH noise. 2.2 Dual-VDD CVS Simulation A Perl-script-based simulator is implemented to estimate power reduction of a dual-VDD CVS system. As illustrated in Fig. 1, the simulator models the initial single-VDD design as a series of paths each of which consists of a chain of fanout-of-four (F04) inverters (IV) sandwiched between two flip-flops. Three different logic depths - 12, 20, and 40 F04 IV unit delays - are employed to evaluate their impact on power saving of a CVS system. Initially, all flip-flops and IVs are VDDH cells. The first step substitutes all VDDH flip-flops with LCFFs. Since all LCFFs investigated are driven by a VDDL-swing clock, this substitution can reduce clocking power significantly [ 121. For negative slack Initial stage (single-V,, design) ****m* *** Flip-flop replacement and IV upsizing e ... TTTT T TTT 164 Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on January 27, 2010 at 20:15 from IEEE Xplore. Restrictions apply.12 - paths caused by the increased delay of LCFFs, the VDDH IVs are equivalent capacitive load connected to the output of each VDDH upsized to maintain the original clock cycle time. The F03- IV remains unchanged. Then, VDDH IVs are replaced with VDDL IVs in each non-critical path until positive slack disappears. This to build the CVS structure. Finally, the simulator calculates the power of the CVS structure and compares it with the power of the ; ’I E29 $8 * 10 2, m- replacement proceeds in reverse order from the end of each path 0) 4 n CL, =7 w6 initial single-VDD design. The impact of different LCFFs and possible using a theoretical approach [3]. different logic depths on power saving is quantified which is not 160 180 200 220 240 260 280 300 D (d-q delay) [PSI 3. LEVEL-CONVERTING FLIP-FLOPS 3.1 Flip-Flop Characterization Metrics Two important metrics to characterize flip-flop timing are d-q delay, D, and race immunity, R [6]. The former parameter consists of setup time, tserup and clk-q delay, t,lk-q while the latter is determined as a difference between tc/k.q and hold time, th& We introduce another timing metric, sampling window S, which is a sum of tsetup and tho/& Average flip-flop energy per clock cycle defined in [6], E, is employed to characterize flip-flop energy. The energy-delay product, EDP [2,6], is calculated from D and E to compare the