Lab 3: 4-bit Up/Down Counter FSM In this lab, you will build two behavioral implementations of 4-bit Up/Down Counter and interface the up/down counter with your binary to 7-segment LED decoder designed in Lab 2. The 4-bit up/down counter has four inputs, Clk, Rst, Enable, UpDown, and a 4-bit output Cnt, represented by the four outputs Cnt3, Cnt2, Cnt1, Cnt0. If Rst is 1, the counter should reset its count value to zero (0000). Otherwise, if Enable is 1, on every clock cycle the counter should count up by one when UpDown is 1 or count down by one when UpDown is 0. Upon reaching the minimum (0) or maximum (15) count, the counter value should wraparound. In other words, when counting up, the counter should wraparound to 0 after 15, and when counting down, the counter should wraparound to 15 after 0. If Enable is 0, the counter should keep its present value. In order to download your 4-bit up/down counter to the Spartan-3E FPGA board, you will need to interface your counter with the binary to 7-segment LED decoder designed in Lab 2. Furthermore, the 50MHz clock integrated within the Spartan-3E FPGA board operates too quickly to be able to view the counter output on the 7-segment LED display. As such, you must also interface with the clock divider component provided with this lab. The clock divider, ClkDiv, has two inputs, Clk and Rst, and one output, ClkOut. Given the 50 MHz clock provided by the Spartan-3E FPGA board, the ClkDiv component will generate a 1 Hz clock on its output, ClkOut. This 1 Hz clock can then be connected to the input of your 4-bit counter. The resulting counter will count up or down once every second if enabled. The figure to the right provides an overview of the connections that will be used to implement your 4-bit Up/Down Counter on the Spartan-3E FPGA board. The overall counter implementation will have a single Clk input provided by the 50 MHz oscillator integrated on the Spartan-3E FPGA Board, two reset inputs – one for the clock divider (DivRst) and one for your 4-bit Up/Down Counter (Rst), and Enable and UpDown inputs connected to your 4-bit Up/Down Counter. The implementation will also interface with your binary to 7-segment LED display using the outputs to the individual segment of the 7-segment LED display. The following is a partial .ucf file providing the connection details for the new inputs and outputs needed for the 4-bit Up/Down Counter (you will need complete the .ucf file to properly connect to the 7-segment LED display): NET "Clk" LOC = "C9"; NET "Rst" LOC = "K17" | PULLDOWN; NET "DivRst" LOC = "D18" | PULLDOWN; NET "Enable" LOC = "N17"; NET "UpDown" LOC = "H18"; # Enter additional connections below In3 In2 In1 In0RstDivRstEnable UpDownClkLab Procedure 1. Behaviorally design the 4-bit Up/Down Counter as a Finite State Machine (FSM). You FSM design should consist of two always procedures. The first always procedure, should implement the state register. The second always procedure should implement the FSM control logic. In the design of the FSM control logic, you must use a case statement to describe the combinational behavior associated with each state. 2. Create a testbench to test your design for correct functionality. Your testbench should be self checking using if statements and the $display task to report any errors during simulation. At a minimum, the self checking testbench should test the following cases: a. Check that counter counts up and down correctly b. Check for correct wraparound functionality for counting up and down c. Check for correct reset behavior from non-zero count value d. Check for correct enable behavior 3. Create a new top-level component that structurally connects your 4-bit Up/Down Counter with the clock divider, ClkDiv, and your binary to 7-segment LED decoder. Complete the provided .ucf file and synthesize your 4-bit Up/Down Counter. Download and test your design on the Spartan-3E FPGA board for correct functionality. At a minimum, you should test the same cases as your self checking testbench. 4. Re-implement the FSM control logic procedure of your counter using Boolean equations for the counter’s outputs and internal next state signals. Simulate your counter design using your self checking testbench. 5. Modify your top-level component to utilize the newly re-implemented counter design. Synthesize and download your modified 4-bit Up/Down Counter to the Spartan-3E FPGA board and test your design for correct functionality. At a minimum, you should test the same cases as your self checking testbench. Demo (you must demo the following aspects to the TA) 1. Behavioral Verilog code for your original 4-bit Up/Down Counter FSM design. 2. Self checking testbench design and simulation waveforms demonstrating correct functionality of the 4-bit Up/Down Counter design for the required test cases. 3. Structural Verilog code for top-level component. Synthesis and implementation of 4-bit Up/Down Counter to Spartan-3E FPGA Board demonstrating correct functionality for the required test cases. 4. Behavioral Verilog code using Boolean equations to implement the FSM control logic procedure of your 4-bit Up/Down Counter FSM design. Simulation waveforms and implementation of 4-bit Up/Down Counter on the Spartan-3E FPGA Board demonstrating correct functionality for the required test cases. Lab Report Requirements (In addition to the standard lab report format) 1. Verilog code for both 4-bit Up/Down Counter implementations, self checking testbench, and structural code integrating your counter with the clock divider and binary to 7-segment LED decoder. 2. Simulation waveforms demonstrating correct functionality of the 4-bit Up/Down Counter for the required test cases. Provide annotations on your testbench to indicate where each test case is evaluated. 3. Complete .ucf file used to implement your design on the Spartan-3E FPGA Board. 4. Comment of any differences in design time and functionality of the two 4-bit Up/Down Counter implementation alternatives. From your experience, provide a brief justification as to which design methodology would be