1ECE 274 - Digital LogicLecture 13 Lecture 13 – RTL Introduction Introduction RTL Design Example2Introduction Chapter 3: Controllers Control input/output: single bit (or just a few) representing event or state Finite-state machine describes behavior; implemented as state register and combinational logic Chapter 4: Datapath components Data input/output: Multiple bits collectively representing single entity Datapath components included registers, adders, ALU, comparators, register files, etc.  This chapter: custom processors Processor: Controller and datapathcomponents working together to implement an algorithm5.1sizeansisCombinationallogicn0s1 s0n1bobiclkState registerFSMinputsFSMoutputsALUComparatorRegister fileRegisterCombinationallogicn0s1 s0n1bobiState registerRegister fileALUDatapathController3RTL Design: Capture Behavior, Convert to Circuit Recall Chapter 2: Combinational Logic Design First step: Capture behavior (using equation or truth table) Remaining steps: Convert to circuit Chapter 3: Sequential Logic Design First step: Capture behavior (using FSM) Remaining steps: Convert to circuit RTL Design (the method for creating custom processors) First step: Capture behavior (using high-level state machine, to be introduced)  Remaining steps: Convert to circuitCa p t ure behav i o rConvert to circuit4RTL Design Method5.25RTL Design Method: “Preview”Example Soda dispenser c: bit input, 1 when coin deposited a: 8-bit input having value of deposited coin s: 8-bit input having cost of a soda d: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda88ascdSodadispenserprocessorascdSodadispenserprocessor25102511500000tot: 25tot: 50How can we precisely describe this processor’s behavior?a6Preview Example: Step 1 --Capture High-Level State Machine Declare local register tot Init state: Set d=0, tot=0 Wait state: wait for coin If see coin, go to Add state Add state: Update total value: tot = tot + a Remember, ais present coin’s value Go back to Wait state In Wait state, if tot >= s, go to Disp(ense) state Disp state: Set d=1 (dispense soda) Return to Init stateInputs: c(bit),a(8 bits),s(8 bits)Outputs: d (bit)Localregisters:tot (8 bits)Wa i tAddDispInitd=0tot=0c’∗(tot<s)d=1ctot=tot+a88ascdSodadispenserprocessorc’∗(tot<s)’7Preview Example: Step 2 -- Create Datapath Need totregister Need 8-bit comparator to compare sand a Need 8-bit adder to perform tot = tot + a Wire the components as needed for above Create control input/outputs, give them namesldclrtot8-bit<8-bitadder8888saDatapathtot_ldtot_clrtot_lt_sInputs :c (bit), a(8 bits), s(8 bits)Outputs : d (bit)Local reg isters: tot (8 bits)WaitAddDispInitd=0tot=0c‘(tot<s)‘c‘∗(tot<s)d=1ctot= tot+a8Preview Example: Step 3 –Connect Datapath to a Controller Controller’s inputs External input c(coin detected) Input from datapathcomparator’s output, which we named tot_lt_s Controller’s outputs External output d(dispense soda) Outputs to datapathto load and clear the totregistertot_lt_stot_clrtot_ldController Datapathscda88ldclrtot8-bit<8-bitadder8888saDatapathtot_ldtot_clrtot_lt_s9Preview Example: Step 4 – Derive the Controller’s FSM Same states and arcs as high-level state machine But set/read datapathcontrol signals for all datapathoperations and conditionstot_lt_stot_clrtot_ldController Datapat hscda88ldclrtot8-bit<8-bitadder8888saDat a pat htot_ldtot_clrtot_lt_sInputs::c,tot_lt_s(bit)Outputs:d,tot_ld,tot_clr(bit)Wa i tDispInitd=0tot_clr=1c’*tot_lt_s’c’*tot_lt_sd=1ctot_ld=1cdtot_ldtot_clrtot_lt_sControllerAdd10Preview Example: Completing the Design Implement the FSM as a state register and logic As in Ch3 Table shown on rightd000000000100000000101111000000n01111110010n100001011000101010100c0011001100s10000000011s00000111101tot_lt_stot_ldtot_clrInitWai tAddDispInputs::c,tot_lt_s(bit)Outputs:d, tot_ld,tot_clr (bit)Wa i tDispInitd=0tot_clr=1c’*tot_lt_s’c’*tot_lt_sd=1ctot_ld=1cdtot_ldtot_clrtot_lt_sControllerAdd11Design Challenge Design Challenge Create a high-level state machine that describes the following system behavior.  The system has an 8-bit input A, a single-bit input d, and a 32-bit output S.  On every clock cycle, if d=1, the system should add A to a running sum and output that sum on S.  If d=0, the system should instead subtract. Ignore issues of overflow and underflow. Don’t forget to include an initialization state.  Hint: declare and use an internal register to keep the sum. (b) Add a 1-bit input rst to the system. When rst=1, the system should clear its sum back to 0. Due:  Next Lecture (Friday, October 17) Extra Credit (Homework) 2