1ECE 274 - Digital LogicBeyond the Book: High-level FSMs Lecture 21 – High-level FSM Custom Processors RTL Design Method2ECE 274 - Digital Logic Introduction to Custom ProcessorsCombinationallogicn0s1 s0n1bobiclkState registerFSMinputsFSMoutputsALUComparatorRegister fileRegisterzeRegister fileALUDatapathControllerCombinationallogicn0s1 s0n1bobiState registerControllers Control input/output: single bit (or just a few) representing event or state FSM describes behavior; implemented as state register and combinational logic Datapath components Data input/output: Multiple bits collectively representing single entity Registers, adders, ALU, comparators, etc.  Custom processors Controller and datapath components working together to implement an algorithm3ECE 274 - Digital Logic RTL Design: Capture Behavior, Convert to Circuit How do we design circuits? Combinational Logic Design First step: Capture behavior (equation or truth table) Remaining steps: Convert to circuit Sequential Logic Design First step: Capture behavior (FSM) Remaining steps: Convert to circuit RTL Design (the method for creating custom processors) First step: Capture behavior (high-level state machine, to be introduced)  Remaining steps: Convert to circuitCapture behaviorConvert to circuit4ECE 274 - Digital Logic RTL Design MethodDescribe the system’s desired behavior as a high-level state machine. The state machine consists of states and transitions. The state machine is “high-level” because the transition conditions and the state actions are more than just Boolean operations on bit inputs and outputsCapture the high-level FSMStep 1:Create a datapath to carry out the data operations on the high-level state machineCreate a datapathStep 2:Connect the datapath to the controller block. Connect external Boolean inputs and output to the controller blockConnect the datapath to the controllerStep 3:Convert the high-level state machine to a finite-state machine (FSM) for the controller, by replacing data operations with setting and reading of control signals to and from the datapathDerive the controller’s FSMStep 4:DescriptionStep5ECE 274 - Digital Logic RTL Design Method: Soda Dispenser Example Soda dispenserc: bit input, 1 when coin depositeda: 8-bit input having value of deposited coins: 8-bit input having cost of a sodad: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a sodaHow can we precisely describe this processor’s behavior?ascdSoda dispenser processor5000total : 0ascdSoda dispenser processor255001total : 25ascdSoda dispenser processor5000total : 25ascdSoda dispenser processor255001total : 50ascdSoda dispenser processor5000total : 50ascdSoda dispenser processor5000total : 0ascdSoda dispenser processor5010total : 50ascdSoda dispenser processor6ECE 274 - Digital LogicRTL Design Method: Soda Dispenser (Step 1) Step 1: Describe behavior using high-level FSM Start with inputs/output of system Declare local register tot Init state Don’t dispense soda (d=0), clear running total (tot=0) Wait state Wait for coin, if see coin go to Add state Add state Update total value: tot = tot + a Remember, ais present coin’s value Go back to Wait state In Wait state If tot < = s, Wait If tot >= s, go to Disp(ense) state Disp state Set d=1 (dispense soda) Return to Init stateInputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit)Local registers: tot (8 bits)c’•(tot<s)d=1Initd=0tot=0WaitAddctot=tot+aDispc’•(tot<s)’88ascdSoda dispenser processor7ECE 274 - Digital Logic RTL Design Method: Soda Dispenser (Step 1) Created a high-level FSM, not an FSM, because Multi-bit (data) inputs aand s Local register tot Data operations tot=0, tot<s, tot=tot+a. High-level state machines are useful, Data types beyond just bits Local registers Arithmetic equations/expressionsInputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit)Local registers: tot (8 bits)c’•(tot<s)d=1Initd=0tot=0WaitAddctot=tot+aDispc’•(tot<s)’8ECE 274 - Digital LogicRTL Design Method: Soda Dispenser (Step 2) Step 2: Create a Datapath What’s going in and out of datapath? Multi-bit values – a, s Need totregister Need 8-bit comparator to compare sand tot Need 8-bit adder to perform tot = tot + aInputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit)Local registers: tot (8 bits)Dispc’*(tot<s)d=1Initd=0tot=0WaitAddctot=tot+ac’*(tot<s)’tot_ldtot_clrldclrtotDatapath8tot_lt_s8-bit<88-bitadder88sa9ECE 274 - Digital LogicRTL Design Method: Soda Dispenser (Step 3) Step 3: connect datapath to controller Controller’s inputs External input c(coin detected) Input from datapath comparator’s output, which we named tot_lt_s Controller’s outputs External output d(dispense soda) Outputs to datapath to load and clear the totregistertot_lt_sclrtotDatapath8-bit<88-bitadder88saController8ldtot_ldtot_clrcd10ECE 274 - Digital Logic RTL Design Method: Soda Dispenser (Step 4)tot_lt_stot_clrtot_ldController Datapathscda88 Step 4: Derive the Controller’s FSM Same states and arcs as high-level state machine Transitions and state assignment are bit operations Set/read datapath control signals for all datapath operations and conditionsInputs: c (bit), tot_lt_s (bit)Outputs: d(bit), tot_ld (bit), tot_clr (bit)d=1d=0ccdtot_ldtot_clrtot_lt_stot_clr=1c’ • tot_lt_s’c’ • tot_lt_stot_ld=1Inputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit)Local registers: tot (8 bits)c’•(tot<s)d=1Initd=0tot=0WaitAddctot=tot+aDispc’•(tot<s)’DispInit WaitAdd11ECE 274 - Digital LogicRTL Design Method: Soda Dispenser (Completing the design) Once we have FSM Implement the FSM as a state register and logic State table shown on rightd000000000100000000101111000000n01111110010n100001011000101010100c0011001100s10000000011s00000111101tot_lt_stot_ldtot_clrInitWai tAddDispInputs: c (bit), tot_lt_s (bit)Outputs: d(bit), tot_ld (bit), tot_clr (bit)d=1d=0ccdtot_ldtot_clrtot_lt_stot_clr=1c’ • tot_lt_s’c’ • tot_lt_stot_ld=1DispInit WaitAdd12ECE 274 - Digital LogicExample: Laser-Based Distance MeasurerObject ofinterestD2D = T sec * 3*108m/secsensorlaserT (in seconds) Laser-based distance measurement Pulse laser, measure time T to sense reflection Laser light travels at speed of light, 3*108 m/sec 