1ECE 274 - Digital Logic Lecture 3 Lecture 3 – Chapter 2.9 to 2.10 Introduction to CAD Tools Introduction to Verilog2Introduction to CAD ToolsNeed for CAD ToolsFx1x2Not feasible to manually design these systems We’ve seen basic examples of synthesizing logic expression/equation to logic circuit Very simple circuits (10’s of gates) Today’s systems consist of millions of gates3Introduction to CAD ToolsMany choices Most systems designed with help of CAD (Computer-Aided Design) Tools Usually packaged into a CAD system to perform tasks such as Design Entry, Synthesis, Optimization, Simulation, Physical Design, Verification, and so on … Many different companies/tools exists today4Introduction to CAD ToolsSimple Design Flow Very basic design flow Design Entry Synthesis and Optimization Simulation Physical DesignDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Design5Introduction to CAD ToolsDesign Entry Design Concept What is the circuit supposed to do? Design Entry General structure of how circuit performs desired function Typically performed by designer Design entry methods Truth tables Schematic Capture Hardware Description LanguageDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Design6Introduction to CAD ToolsDesign Entry with Truth Tables Design entry using truth tables Text file Waveform Editor Practical only for small designs or subcircuitsDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical DesignF = x1’ + x2x1 x2 F01 100 110 011 10 0 10 1 11 0 01 1 17Introduction to CAD ToolsDesign Entry with schematic capture Design entry using schematic capture Graphical tool where designer uses mouse to draw circuit diagram Library of basic gates designer chooses from Designer specifies interconnections Enables hierarchical design Smaller circuits represented by graphical symbol and used in larger circuits Compared to truth tables, better for larger designs Still has limitationsDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Design8Introduction to CAD ToolsDesign Entry with HDLs Design entry using HDLs (Hardware Description Language) Similar to a computer program Describes underlying hardware implementation Many HDLs exits, two main ones Verilog VHDL (Very High Speed Integrated Circuit HDL) Advantages Widely supported Enables portability Underlying implementation can differ without having to change the design specification Text-based Easy to include in documentation Modular implementation possible Enables hierarchical implementation of circuits Sharing and re-useDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Design9Introduction to CAD ToolsSynthesis and Optimization Synthesis performed by CAD tool Translate design entry into intermediate format We assume logic function (for simplicity) Realistically intermediate formats vary depending on tool  Likely designer did not optimally specify designLogic synthesisor logic optimizationperformed by synthesis tool Important task of manipulating user’s design to produce equivalent, but better circuit What makes circuit “better”? Size/area, performance, cost, etc …Design ConceptDesign EntrySynthesis and OptimizationSimulationPhysical DesignG1G1 = wx + wy + zw xwy zwxyz G2G2 = w(x + y) + zcost = 3 + 7 = 10cost = 3 + 6 = 9delay = 2delay = 310Introduction to CAD ToolsFunctional Simulation How do we know our design actually works? Functional Simulation Method Designer provides input values Functional simulator applies these values to the equations Functional simulator produces correspond outputs Truth table or timing diagram User examines output to verify design Gate DelayFunctional simulatorassumes delay negligibleTiming simulatoraccounts for timing details related to a specific technologyDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Design1 0 1 0 1 0 x1 x2 f Timex1 x2 f 11Introduction to CAD ToolsPhysical Design Physical Design is a type of synthesis Sometimes referred to as layout synthesis Implement the intermediate format into a technology dependent formatDesign ConceptDesign EntrySynthesis and OptimizationSimulationPhysical Designf = (a + b) · (c + d) · (e · f)Spartan 3 FPGA BoardCustom ICPentium processorCoolRunner-II FPGA Board12Introduction to CAD ToolsExpanded Design Flow – First Stages of a Typical CAD System Expanded design flow Preliminary stages Designer can use mixture of design entry methods Automatically merged into one specification Iterative processDesign conception Truth table VerilogSchematic capture Simple synthesis (see section 2.8.2)Translation Merge Boolean equations INITIAL SYNTHESIS TOOLS DESIGN ENTRYDesign correct? Logic synthesis, physical design, timing simulation Functional simulation NoYes (see section 4.12)13Introduction to VerilogRepresenting Digital Circuits with an HDL Previously discussed different ways for design entry Truth table, schematic capture, HDL Labs will use HDLs, specifically Verilog Let’s look at how to specify circuits in Verilog Appendix A in book provides reference Many website provide good tutorials14Introduction to VerilogPrimitives Verilog includes a set of gate level primitivescorresponding to commonly used logic gatesor (out, in1, in2);not (out, in);More primitivesnand (out, in1, in2);nor (out, in1, in2);xor (out, in1, in2);xnor (out, in1, in2);everything after // to end of line is a commentand (y, x1, x2); // 2-input AND gatekeyword that specifies gate typespecifies input, x1 and x2specifies output, yand (f, a, b, c); // 3-input AND gateand (out, in1, in2, in3, in4); // 4-input AND gate15Introduction to VerilogExample 1 Using primitives let’s implement a circuit in Verilogfx3x1x2fx3x1x2example1// example1.vmodule example1 (x1, x2, x3, f);endmodulemodule indicates the start of our specification, endmoduleindicates the endwe have a “black box”named example1“black box” has 4 ports – x1, x2, x3, f16Introduction to VerilogExample 1fx3x1x2// example1.vmodule example1 (x1, x2, x3, f);input x1, x2, x3;output f;endmoduleinput statement indicates x1, x2, and x3 are inputs to the systemsoutput statement indicates f is an output of the systemfx3x1x2example117Introduction to