1ECE 274 - Digital LogicBeyond the Book: High-level FSMs Lecture 22 – High-level FSM (continued) New Component - Register Files Interfacing with Register Files RTL Pitfalls and Good Practice2ECE 274 - Digital Logic Register Files8888xyData from the car’s computeri0i1i2i38Dds1 s08-bit4×1To the above mirror displayC8a0a1loadloadreg0 (T)loadreg1 (A)loadreg2 (I)loadreg3 (M)d0d1d2d3ei0i12×4Back to above the mirror display Write to and read from four 8-bit registers Need access one or two at a time3ECE 274 - Digital Logic Register Files Inefficient implementation Too many wires MUX becomes large and slow Only worsens with more/larger registers What if we wanted 16 32-bit registers? 8888xyData from the car’s computeri0i1i2i38Dds1 s08-bit4×1To the above mirror displayC8a0a1loadloadreg0 (T)loadreg1 (A)loadreg2 (I)loadreg3 (M)d0d1d2d3ei0i12×488-bit 4x1 muxDi0i1x1x2i2i3x3x4s1s04ECE 274 - Digital Logic Register Files Register File Provides efficient access to M N-bit-wide registers Component that has one data input and one data output Multiple input/output ports also possible Allows us to specify which internal register to write and which to readfx1fx1when e=1, f =xwhen e = 0, f = “z”f = x fxeTri-state bufferfxDriver/buffer5ECE 274 - Digital Logic Register File324324W_dataW_addrW_enR_dataR_addrR_en4×32register file Register file block diagram provided 4 registers Each register is 32-bits 1 write port, 1 read port To write data W_data = data value to be stored W_addr = address where data will be stored W_en = when 1, writes data To read data R_data = contains data value read R_addr = address where data will be read from R_en = when 1, reads data6ECE 274 - Digital Logic Register File Timing Diagram0:1:2:3:???90:1:2:3:?22?90:1:2:3:?22?90:1:2:3:?22?90:1:2:3:?2217790:1:2:3:?221775550:1:2:3:????93ZX221XXX23X 177 555ZZ Z9 9 55522XX331cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6clkW_d at aR_ d a t aW_ad drR_addrW_e nR_en123654322322W_dataW_addrW_enR_dataR_addrR_en4x32register file Can write one register and read one register each clock cycle May be same registerWrite occurs on rising edge of clk cycle (+ small delay) because we wait for registerRead occurs independent of rising edge of clk cycle, only wait for read decoder7ECE 274 - Digital Logic RTL Example: Video Compression – Sum of Absolute Differences Try example using register file Video is a series of frames (e.g., 30 per second) Most frames similar to previous frame Compression idea: just send difference from previous frameDigitizedframe 21 MbyteFrame 2Digitizedframe 1Frame 11 MbyteOnly difference: ball movingDigitizedframe 1Frame 11 MbyteDifference of2 from 10.01 MbyteFrame 2Just send difference8ECE 274 - Digital Logic RTL Example: Video Compression – Sum of Absolute DifferencesFrame 2Frame 1compareEach is a pixel, assume represented as 1 byte(actually, a color picture might have 3 bytes per pixel, for intensity of red, green, and blue components of pixel) Build Sum of Absolute Differences (SAD) Circuit Quickly determine whether two frames are similar enough to just send difference for second frame, or need to send second frame itself If above a threshold Send complete frame for second frame If below a threshold Use difference method (using another technique, not described)9ECE 274 - Digital Logic RTL Example: Video Compression – Sum of Absolute DifferencesFrame 2Frame 1compareEach is a pixel, assume represented as 1 byte(actually, a color picture might have 3 bytes per pixel, for intensity of red, green, and blue components of pixel) SAD Circuit Procedure Consider frame a 256-byte array (256 x 8 Register File) Each byte represents a pixel (color) For each pixel, determine difference in color of frame 1 and frame 2 Difference for a single pixel = |frame 1 – frame2| Sum those differences Difference between frames, sum = sum + |frame1 – frame2| Sum > threshold, send complete frame for second frame Sum < threshold, send difference between frames10ECE 274 - Digital LogicRTL Example: Video Compression – Sum of Absolute Differences Want fast sum-of-absolute-differences (SAD) component When go=1, sums the differences of element pairs in arrays Aand B, outputs that sum256-byte array(Frame 1)256-byte array(Frame 1)goSADsadinteger8Register File AR_addrR_enR_dataA_data8Register File BR_addrR_enR_dataB_dataAB_addrAB_en911ECE 274 - Digital LogicRTL Example: Video Compression – Sum of Absolute Differences Step 1: Create high-level state machine S0 -wait for go S1- initialize sumand index S2 - check if done (i>=256) S3 - add difference to sum, increment index S4 - done, write to output sad_regInputs: A, B (256 byte Reg File); go (bit)Outputs: sad (32 bits)Local registers: sum, sad_reg (32 bits); i (9 bits)!goS0goS1sum = 0i = 0S3sum=sum+abs(A[i]-B[i])i=i+1S4sad_ reg = sumS2i<256(i<256)’goSADsadinteger8Register File AR_addrR_enR_dataA_data8Register File BR_addrR_enR_dataB_dataAB_addrAB_en912ECE 274 - Digital LogicRTL Example: Video Compression – Sum of Absolute Differences Step 2: Create datapathInputs: A, B (256 byte Reg File); go (bit)Outputs: sad (32 bits)Local registers: sum, sad_reg (32 bits); i (9 bits)!goS0goS1sum = 0i = 0S3sum=sum+abs(A[i]-B[i])i=i+1S4sad_ reg=sumS2i<256(i<256)’i_incsad_reg_ldDatapathsumsad_regii_clrsum_clri_lt_256< 256A_data B_data8 8sad32AB_addr9sum_ld32328832–+abs13ECE 274 - Digital LogicRTL Example: Video Compression – Sum of Absolute Differences Step 3: Connect to controller Step 4: Replace high-level state machine by FSMi_lt_256i_inci_clrsum_ldsum_clrsad_reg_ldDatapathsumsad_regsadAB_addr A_data B_data< 256932888 8323232i–+abs!goS0goS1sum = 0i = 0S3sum=sum+abs(A[i]-B[i])i=i+1S4sad_ reg=sumS2i<256(i<256)’Controllergo AB_ rdsum_clr=1i_clr=1i_lt_256i_inc=1i_lt_256’sum_ld=1; AB_rd=1sad_reg_ld=114ECE 274 - Digital LogicRTL Example: Video Compression – Sum of Absolute Differences Software vs. custom circuit SAD  Software Loop (for i = 1 to 256), for each i Move memory to local registers Subtract Compute absolute value Add to sum Increment i About 6 cycles per item, 256*6 = 1536 cycles Custom Circuit Loop (for i = 1 to 256), for each i State S2 check index State S3 performs SAD operation 1 cycle per state, 256*2 = 512 clock cyclesCustom circuit is about 3