1ECE 274 - Digital LogicLecture 6 Lecture 6 Basic Register Design Controllers State diagrams Finite State Machines (FSMs) Sequential Logic Design Process2Digital DesignSequential Logic Design – Controllers: Registersblock symbol.internal design Basic 4-bit register: inputs: n-data bits, clock outputs: n-data bits3Digital DesignSequential Logic Design – Controllers: Design ExampleCircuit Description: Temperature History StorageFunctional Description:Design a system that records the outside temperature every hoursand displays the last three recorded temperatures. Inputs:c: clock signalx4..0: 5-bit temperature readingOutputs:a4..0, b4..0, c4..0: 5-bit temperature readings to be displayed4Digital DesignSequential Logic Design -- ControllersInternal design of the TemperatureHistoryStorage component5Digital DesignSequential Logic Design -- ControllersExample of values in the TemperatureHistoryStorage registers. One particular data item, 18, is shown moving through the registers on each clock cycle.6Digital DesignSequential Logic Design – Controllers: Not really a quiz!!Trace the behavior of a level-sensitive SR latch for the input pattern above. Complete the timing diagram, assuming the logic gates have a tiny but non-zero delay.7Digital DesignSequential Logic Design – Controllers: FSMCircuit Description: Laser Timer SystemFunctional Description:Design a system that activates a laser for exactly 30 ns after it receives a button press. Inputs:c: 10 ns clock signalb: button signalOutputs:x: laser output8Digital DesignSequential Logic Design -- ControllersFirst (bad) attempt to implement the laser surgery system.What’s so baaaaad about it?9Digital DesignSequential Logic Design -- Controllers: FSMA simple state diagram and the timing diagram describing the state diagram’s behavior.“clk^” represents the rising edge of the clock signal10Digital DesignSequential Logic Design -- Controllers: FSMstate diagramtiming diagramThree-Cycle High System - Finite State Machine Set of States; i.e. {Off, On1, On2, On3} Set of Inputs/Outputs; i.e. {}/{x} Initial State: i.e. {Off} Set of Transitions (conditions): (state:input->new state) {Off:!clk^->Off, Off:clk^->On1, On1:clk^->On1…} Set of Actions (output values): {Off:x=0, On1:x=1, On2: x=1, On3: x=1}11Digital DesignSequential Logic Design -- Controllers: FSMstate diagramtiming diagramThree-Cycle High System - Finite State Machine Set of States; i.e. {Off, On1, On2, On3} Set of Inputs/Outputs; i.e. {b}/{x} Initial State: i.e. {Off} Set of Transitions (conditions): (state:input->new state) {Off:b’*!clk^->Off, Off:b*clk^->On1, On1:clk^->On1…} Set of Actions (output values): {Off:x=0, On1:x=1, On2: x=1, On3: x=1}12Digital DesignSequential Logic Design -- Controllers: FSMSimplification in Notation: implicit clk^ every transition is ANDed with a rising clock.13Digital DesignSequential Logic Design -- ControllersWhy are the heads of keys getting thicker? The key on the right has a computer chip inside that sends an identifier to the car’s computer, thus helping to reduce car thefts.14Digital DesignSequential Logic Design – Controllers: FSMCircuit Description: Secure Car KeyFunctional Description:Design a secure car key controller for a key having a code of 1011Inputs: clock assumeda: 1 when the car’s computer requests the key IDOutputs:r: individual bits of key code (starting with rightmost bit)15Digital DesignSequential Logic Design -- ControllersSecure car key FSM.16Digital DesignSequential Logic Design -- ControllersSecure car key timing diagram.17Digital DesignSequential Logic Design -- ControllersSecure car key timing diagram for a different sequence of values on input a.18Digital DesignSequential Logic Design – Controllers: FSMCircuit Description: Code DetectorFunctional Description:Design a system that unlocks a door once is has received the correct sequence of colored buttonsInputs: clock assumedbuttons: r(red), g(green), b(blue): 1 when button of corresponding color is pressed; 0 otherwise– assume presses synchronized with clocka(any): 1 if any button(s) have been pressed (while pressed)Outputs:u: signal to unlock door19Digital DesignSequential Logic Design – Controllers: FSM DesignBuild an FSM to Detect Sequence:Start->Red->Blue->Green->RedYou can press all three buttons at the same time, and the door will unlock20Digital DesignSequential Logic Design – Controllers: FSM DesignImproved code detector FSMBetter, but still flawed: a=r=g=b=1, ab=1, a(b’+r+g)=121Digital DesignSequential Logic Design – Controllers: ImplementationStandard controller architecture -- general view22Digital DesignSequential Logic Design – Controllers: Design Process23Digital DesignSequential Logic Design – Controllers: FSMCircuit Description: Laser Timer SystemFunctional Description:Design a system that activates a laser for exactly 30 ns after it receives a button press. Inputs:c: 10 ns clock signalb: button signalOutputs:x: laser output24Digital DesignSequential Logic Design -- Controllers: FSM1) Capture the FSM:25Digital DesignSequential Logic Design – Controllers: ImplementationStandard controller architecture for the laser timer.2) Create the Architecture:26Digital DesignSequential Logic Design -- Controllers : ImplementationLaser timer state diagram with encoded states.3) Encode the States:27Digital DesignSequential Logic Design -- Controllers : Implementation4) Create the State Table:State table for laser timer controller28Digital DesignSequential Logic Design -- Controllers : Implementation5) Implement Combinational Logic:Final implementation of the three-cycles-high laser timer controller.29Digital DesignSequential Logic Design -- Controllers : ImplementationTracing the behavior of the three-cycles-high laser timer controller.30Digital DesignSequential Logic Design -- Controllers31Digital DesignSequential Logic Design -- ControllersOriginal secure car key FSM.32Digital DesignSequential Logic Design -- ControllersSecure car key FSM with encoded states33Digital DesignSequential Logic Design -- ControllersState table for secure car key controller34Digital DesignSequential Logic Design -- ControllersAn unknown standard controller architecture.35Digital DesignSequential Logic Design -- ControllersState table for unknown controller.36Digital DesignSequential Logic Design -- Controllers Converting a state table to an FSM diagram (a) Initial FSM (b) FSM