ECE 274 – Homework Assignment 4 Due at the beginning of class – Wednesday March 28, 2007 1. (5 points) Show the multiplication of two signed numbers represented in two’s complement. Be sure to show the partial product as well as the final product. a. 0102 * 0112 (210 * 310) b. 1102 * 0112 (-210 * 310) 2. (5 points) Trace the outputs appearing at the output of a 3-bit carry-ripple adder for every one FA delay time period when adding 111 with 011. Assume all previous inputs were zero for a long time. 3. (5 points)Trace through the execution of a 4-bit magnitude comparator when a=15 and b=12. Be sure to show how the comparisons propagate through the individual comparators. 4. (5 points) Design a special multiplier circuit that can multiply it’s 16-bit input by 1,2, 4, 8, 16, or 32 specified by 3 inputs a, b, and c. A input of abc=000 means no multiply, abc=001means multiply by 2, abc=010 means multiply by 4, abc=011 means by 8, abc=100 means16, and abc=101 means by 32. HINT: You do not need to design a custom multiplier circuit, rather you can utilize other combinational components. Simply show the block-level diagram and the corresponding interconnections. 5. (10 points) Design a 3-bit ALU to perform the operations specified. Inputs a b Operation 0 0 Clear output to 0 0 1 A – B 1 0 B + 2 1 1 B 6. (5 points) Trace the execution of a level sensitive SR Latch for the following input pattern. Assume S1, R1, and Q are initially 0. Complete the timing diagram assuming logic gates have a tiny but non-zero delay C S R S1 R1 Q 7. (5 points) Trace the execution of a D Latch for the following input pattern. Assume Q is initially 0. Complete the timing diagram assuming logic gates have a tiny but non-zero delay C D S R Q8. (5 points) Compare the behavior of D latch and D flip-flop devices by completing the timing diagram below. Assume each device initially stores a 0. Provide a brief explanation of the behavior of each device. C D Q (D latch) Q (D flip-flop) 9. (10 points) Design a 4-bit multifunction register, defined by the table below. Each input should have its own control line. Inputs SHL ROL CLR INV Operation 0 0 0 0 Maintain present value 0 0 0 1 Invert input, Q = I' 0 0 1 X Clear, Q = 0 0 1 X X Rotate Left 1 X X X Shift Left 10. (5 points) Draw a state diagram for an FSM that has an input X and an output Y. Whenever X changes from 0 to 1, Y should become 1 for two clock cycles and then return to 0 – even if X is still 1. Remember that in an FSM, every transition condition is implicitly ANDed with a rising clock edge. SHLROLCLRSHL_ININVI3 I2 I1 I0 Q3 Q2 Q1
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