1ECE 274 - Digital LogicLecture 15 Lecture 15 – RTL Design Four Step RTL Design Method RTL Examples2Step 2: Create a Datapath Datapath must Implement data storage Implement data computations Look at high-level state machine, do three substeps (a) Make data inputs/outputs be datapathinputs/outputs (b) Instantiate declared registers into the datapath (also instantiate a register for each data output) (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computationsInstantiate: to introduce a new component into a design.3Step 2 Example: Laser-Based Distance Measurer(a) Make data inputs/outputs be datapathinputs/outputs(b) Instantiate declared registers into the datapath(also instantiate a register for each data output)(c) Examine every state and transition, and instantiate datapathcomponents and connections to implement any data computationsDatapathDreg_clrDctr_clrDctr_cntDreg_ldLocal Registers: Dctr (16 bits)S0S1 S2 S3L = 0D = 0L = 1 L=0Dctr = Dctr + 1Dctr = 0B‘S‘BSD = Dctr / 2(calculate D)S4loadQIDreg: 16-bitregisterQDctr: 16-bitup-counter16DclearclearcountaInputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)4Step 2 Example: Laser-Based Distance Measurer(c) (continued) Examine every state and transition, and instantiate datapathcomponents and connections to implement any data computationsclearcountclearloadQQIDctr: 16-bitup-counterDreg: 16-bitregister16DDatapathDreg_clrDctr_clrDctr_cntDreg_ld1616>>1aLocal Registers: Dctr (16 bits)S0S1 S2 S3L = 0D = 0L = 1 L=0Dctr = Dctr + 1Dctr = 0B‘S‘BSD = Dctr / 2(calculate D)S4Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)5Step 2 Example Showing Mux Use Introduce mux when one component input can come from more than one sourceT0T1R = E + FR = R + GE, F, G, R (16 bits)Lo c a lr eg i st e r s:(a)EFGAB+Radd_A_s0add_B_s02⋅1 2⋅1(d)××aEFGAB+R(b)EFGAB+R(c)6Step 3: Connecting the Datapath to a Controller Laser-based distance measurer example Easy – just connect all control signals between controller and datapath300 MHz ClockDBLS16to displayfrom buttonControllerto laserfrom sensorDatapathDreg_clrDreg_ldDctr_clrDctr_cntclearcountclearloadQQIDctr: 16-bitup-counterDreg: 16-bitregister16DDatapathDreg_clrDctr_clrDctr_cntDreg_ld7Step 4: Deriving the Controller’s FSM FSM has same structure as high-level state machine Inputs/outputs all bits now Replace data operations by bit operations using datapath300 MHz ClockDBLS16to disp layfrom buttonCont r o l l e rto lase rfrom sensorDatapathDreg_clrDreg_ldDct r _ c l rDct r _ cntInputs: B, SOutputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cntS0S1 S2 S3L = 0 L = 1 L = 0L = 0B’S’BSS4L = 0Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)Local Registers: Dctr (16 bits)S0S1 S2 S3L = 0D = 0L = 1 L=0Dctr = Dctr + 1Dctr = 0B’S’BSD = Dctr / 2(calculate D)S4aDreg_clr = 1Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 0(laser off)(clear D reg)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 1Dctr_cnt = 0(clear count)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 0(laser on)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 1(laser off)(count up)Dreg_clr = 0Dreg_ld = 1Dctr_clr = 0Dctr_cnt = 0(load D reg with Dctr/2)(stop counting)8Step 4: Deriving the Controller’s FSM Using shorthand of outputs not assigned implicitly assigned 0aS0 S1 S2 S3L = 0 L = 1 L = 0L = 0B’S’BSS4L = 0Dreg_clr = 1Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 0(laser off)(clear D reg)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 1Dctr_cnt = 0(clear count)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 0(laser on)Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_cnt = 1(laser off)(count up)Dreg_clr = 0Dreg_ld = 1Dctr_clr = 0Dctr_cnt = 0(load D reg with Dctr/2)(stop counting)S0S1 S2 S3L = 0 L = 1 L = 0B’S’BS(laser on)S4Inputs: B, SOutputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cntDreg_clr = 1(laser off)(clear D reg)Dctr_clr = 1(clear count)Dctr_cnt = 1(laser off)(count up)Dreg_ld = 1Dctr_cnt = 0(load D reg with Dctr/2)(stop counting)9Step 4 Implement FSM as state register and logic (Ch3) to complete the designclearcountclearloadQQIDctr: 16-bitup-counterDreg: 16-bitregister16DDatapathDreg_clrDctr_clrDctr_cntDreg_ld300 MHz ClockDBLS16to displayfrom buttonControllerto laserfrom sensorDatapathDreg_clrS0 S1 S2 S3L = 0 L = 1 L = 0B’S’BS(laser on)S4Inputs: B, SOutputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cntDreg_clr = 1(laser off)(clear D reg)Dctr_clr = 1(clear count)Dctr_cnt = 1(laser off)(count up)Dreg_ld = 1Dctr_cnt = 0(load D reg with Dctr/2)(stop counting)Dreg_ldDctr_clrDctr_cnt10RTL Design Examples and Issues We’ll use several more examples to illustrate RTL design Example: Bus interface Master processor can read register from any peripheral Each register has unique 4-bit address  Assume 1 register/periph. Sets rd=1, A=address Appropriate peripheral places register data on 32-bit Dlines Periph’s address provided on Faddrinputs (maybe from DIP switches, or another register)324ArdDPer0 Per1 Per15MasterprocessorFaddr4ADrdBus interfaceMain partPeripheralQ32to/from processor bus32411RTL Example: Bus Interface Step 1: Create high-level state machine State WaitMyAddress Output “nothing” (“Z”) on D, store peripheral’s register value Qinto local register Q1 Wait until this peripheral’s address is seen (A=Faddr) and rd=1 State SendData Output Q1onto D, wait for rd=0(meaning main processor is done reading the Dlines)WaitMyAddressInputs: rd (bit); Q (32 bits); A, Faddr (4 bits)Outputs: D (32 bits)Local register: Q1 (32 bits)rd’rdSendDataD = “Z”Q1 = Q(A = Faddr)and rd((A = Faddr)and rd’)D = Q112RTL Example: Bus InterfaceWWZDZZQ1 Q1WW WSD SD SDclkInputsSt a t eOut pu tsrdWaitMyAddressInputs: rd (bit); Q (32 bits); A, Faddr (4 bits)Outputs: D (32 bits)Local register: Q1 (32 bits)rd’rdSendDataD = “Z”Q1 = Q(A = Faddr)and rd((A = Faddr)and rd’)D = Q113RTL Example: Bus InterfaceWaitMyAddressInputs: rd (bit); Q (32 bits); A, Faddr (4 bits)Outputs: D (32 bits)Local register: Q1 (32 bits)rd’rdSendDataD = “Z”Q1 = Q(A = Faddr)and rd((A = Faddr)and rd)’D = Q1 Step 2: Create a datapath(a) Datapath inputs/outputs(b) Instantiate declared registers(c) Instantiate datapath components and connectionsDatapathBus interfaceQ1_ldldQ1FQaddr44 32AD_enA_eq_Faddr= (4-bit)3232Da14RTL Example: Bus Interface Step 3: Connect datapath to controller Step 4: Derive controller’s FSMaWaitMyAddressInputs: rd (bit);