1ECE 274 - Digital LogicChapter 6: Combinational-Circuit Building Blocks Lecture 15 Encoders  Code Converter Comparators Equality Comparators ** Magnitude (Arithmetic) Comparators Shifters ** Incrementors ** Arithmetic-Logic Units (ALU) **** Additional Components not included in textbook2ECE 274 - Digital Logic Encoder Encoder Opposite of Decoder Converts “One-hot encoded”number to more compact output 4-to-2 Encoder 4 inputs, 2 outputs Internal design F0 = A1 + A3 F1 = A2 + A3Remaining combinations in truth table are treated as don’t cares4-to-2 EncoderF0F1A0A1A2A3000001F0F1A0A1A2A3001100F0F1A0A1A2A3010010F0F1A0A1A2A3111000A3 A200000110A1 A001100000F10011F00101F0F1A0A1A3A23ECE 274 - Digital Logic Priority Encoder Priority Encoder Each input assigned a priority level Output indicates the active input (=1) with the highest priority If no active input, indicated by extra output Z set to 1 Assume A3 has highest priority, then A2, A1, A0 Truth table shown Internal design F0 = A1 + A3 F1 = A2 + A3Remaining combinations in truth table are treated as don’t cares4-to-2 Priority EncoderA3 A200011xA1 A01xxxxxF1011F0101Z11100010010000dd0F0A0A1A2A300101F11Z1F0A0A1A2A311111F11Z1F0A0A1A2A300000F10Z1x – shorthand denoting all possible combinationsd - indicates don’t care4ECE 274 - Digital Logic Code Converter Decoders Converts binary number to “one-hot” output encoding Encoders Converts “one-hot” output encoding to binary number Code Converters Many other types of encoding schemes Example: BCD-to-7 Segment Display Type of decoder, though decoder typically reserved for “one-hot” output encodingsafbdgec4-to-2 EncoderF0F1A0A1A2A3000001F0F1A0A1A2A3001100F0F1A0A1A2A3010010F0F1A0A1A2A31110002-to-4 Decoderi0i1d0d1d2d3 111000i0i1d0d1d2d3 000001i0i1d0d1d2d3i0i1d0d1d2d30010100101005ECE 274 - Digital Logic Equality Comparator N-bit equality comparator Outputs 1 if two N-bit numbers are equal 4-bit equality comparator with inputs A and B For equality to be true a3=b3, a2 = b2, a1 = b1, a0 = b0 Two bits are equal if both 1, or both 0 eq = (a3b3 + a3’b3’) · (a2b2 + a2’b2’) ·(a1b1 + a1’b1’) · (a0b0 + a0’b0’) XNOR outputs 1 if its two input bits are the same eq = (a3 xnor b3) · (a2 xnor b2) ·(a1 xnor b1) · (a0 xnor b0)a3 b3 a2 b2 a1 b1 a0 b0eq(a)a3 a2 a1 a0 b3eqb2 b1 b04-bit equality comparator0110 = 0111 ?01100111011106ECE 274 - Digital Logic Magnitude Comparator N-bit magnitude (arithmetic) comparator Two N-bit inputs A and B Indicates whether A>B, A=B, or A<B Implementation? XNOR function will tell us if bits are equal in= anxnor bnA = B, if all bits equal AeqB = i3i2i1i0A > B AgtB = a3b3’ + i3a2b2’ + i3i2a1b1’ + i3i2i1a0b0’ a3= 1, b3= 0 (a3b3’)  a3= b3and a2=1, a2=1 (i3a2b2’) and so on … A < B If A≠B and (A>B)’ then must be A<B AltB = (AeqB + AgtB)’a3 a2a1 a0b3 b2b1 b0AgtBAeqBAltB4-bit magnitude comparatorA=1011 B=1001100i0i1i2i3b0a0b1a1b2a2b3a3AeqBAgtBAltB7ECE 274 - Digital Logic Magnitude Comparator Alternative Implementation Consider how compare by hand First compare a3 and b3 If equal, compare a2 and b2 And so on Stop if comparison not equal --whichever bit is 1 is greater.  If never see unequal bit pair, A=B. A=1011 B=10011011 1001 Equal1011 1001 Equal10111001 UnequalSo A > B8ECE 274 - Digital Logic Magnitude Comparator By-hand example leads to idea for design Start at left, compare each bit pair, pass results to the right Each bit pair called a stage Each stage has 3 inputs indicating results of higher stage, passes results to lower stagein_gtin_eqin_ltout_gtout_eqout_ltIgtIeqIltStage 3a3 b3abin_gtin_eqin_ltout_gtout_eqout_ltStage 2a2 b2abin_gtin_eqin_ltout_gtout_eqout_ltStage 1a1 b1abin_gtin_eqin_ltout_gtout_eqout_ltAgtBAeqBAltBStage 0a0 b0ab9ECE 274 - Digital Logic Magnitude Comparator Each stage: out_gt= in_gt+ (in_eq·a ·b’) A>B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0 out_lt = in_lt + (in_eq · a’ · b) A<B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=0 and b=1 out_eq = in_eq · (a XNOR b) A=B (so far) if already determined in higher stage and in this stage a=b tooin_gtin_eqin_ltout_gtout_eqout_ltIgtIeqIltStage 3a3 b3abin_gtin_eqin_ltout_gtout_eqout_ltStage 2a2 b2abin_gtin_eqin_ltout_gtout_eqout_ltStage 1a1 b1abin_gtin_eqin_ltout_gtout_eqout_ltAgtBAeqBAltBStage 0a0 b0ab10ECE 274 - Digital Logic Magnitude Comparator Internal Circuit Diagramin_gtin_eqin_ltout_gtout_eqout_ltStage xax bxab Simple circuit inside each stage out_gt= in_gt+ (in_eq·a ·b’) out_eq = in_eq · (a XNOR b) out_lt = in_lt + (in_eq · a’ · b)in_ltin_eqin_gtb3a3out_gtout_ltout_eq11ECE 274 - Digital Logic Magnitude Comparator In Action How does it work? Final answer appears on the right Takes time for answer to “ripple” from left to right Called “carry-ripple style” after the carry-ripple adder, even though there’s no “carry” involved1 1 0 0 1 0 1 10100101011 = 1001 ?010Ieq=1 causes this stage3 to compare===100010in_gtin_eqin_ltout_gtout_eqout_ltIgtIeqlltStage 3a3 b3abin_gtin_eqin_ltout_gtout_eqout_ltStage2a2 b2abin_gtin_eqin_ltout_gtout_eqout_ltStage1a1 b1abin_gtin_eqin_ltout_gtout_eqout_ltAgtBAeqBAltBStage0a0 b0ab12ECE 274 - Digital Logic Minimum Circuit Detect Implementation Using a Magnitude Comparator Design a combinational component that computes the minimum of two 8-bit numbers Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux If A<B, pass A through mux. Else, pass B. 11000000 0111111100101111111MINIgtIeqIltAgtBAeqBAltB010AABB8-bit magnitude comparatorsI1 I02x1 mux8-bitC8888 8888CABMin13ECE 274 - Digital Logic Left Shifter Left Shift Shift left once is same as multiplying by 2 0011 (3) becomes 0110 (6) Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just be appending 0, i.e., by shifting left (55 becomes 550)i2q3 q2 q1 q0ini3 i1 i0Left shifter (just wires)01 01 01 01inshli3q3 q2 q1 q0i2 i1 i0Shifter with left shift or no shift using MUXes<<1Symbol14ECE 274 - Digital Logic Right Shifter Shift Right Shift right once same as dividing by 2 1000 (8) becomes 0100 (4)i2q3 q2 q1 q0ini3 i1