1ECE 274 - Digital LogicLecture 7 Lecture 7 Sequential Logic Design Common Pitfalls Additional Topics2Digital DesignCommon Pitfalls Regarding Transition PropertiesOnlyone condition should be true For all transitions leaving a state Else, which one?Onecondition must be true For all transitions leaving a state Else, where go?abab=11 –next state?aa’bawhat ifab=00?aa’ba’b’a’ba3Verifying Correct Transition Properties Can verify using Boolean algebra Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0 --> proves pair can never simultaneously be true One condition true: OR of all conditions of transitions leaving a state) should equal 1 --> proves at least one condition must be true Exampleaa’ba + a’b= a*(1+b) + a’b= a + ab + a’b= a + (a+a’)b= a + bFails! Might not be 1 (i.e., a=0, b=0)aQ: For shown transitions, prove whether:* Only one condition true (AND of each pair is always 0)* One condition true (OR of all transitions is always 1)a * a’b= (a * a’) * b= 0 * b= 0OK!Answer:4Simplifying Notations FSMs Assume unassigned output implicitly assigned 0 Sequential circuits Assume unconnected clock inputs connected to same external clocka=0b=1c=0a=0b=0c=1b=1 c=1clk aaa5More on Flip-Flops and Controllers Other flip-flop types SR flip-flop: like SR latch, but edge triggered JK flip-flop: like SR (S-->J, R-->K) But when JK=11, toggles 1-->0, 0-->1 T flip-flop: JK with inputs tied together Toggles on every rising clock edge Previously utilized to minimize logic outside flip-flop Today, minimizing logic to such extent is not as important D flip-flops are thus by far the most common3.56Non-Ideal Flip-Flop Behavior Can’t change flip-flop input too close to clock edge Setup time: time that D must be stable beforeedge Else, stable value not present at internal latch Hold time: time that D must be held stable afteredge Else, new value doesn’t have time to loop around and stabilize in internal latchclkDclkDset up t imehold timeRSDCuD latchQQ’1234567CDSuRQ’QSetup time violationLeads to oscillation!7Metastability Violating setup/hold time can lead to bad situation known as metastablestate Metastable state: Any flip-flop state other than stable 1 or 0 For internal circuits, we can make sure observe setup time But what if input comes from external (asynchronous) source, e.g., button press? Partial solution Insert synchronizer flip-flop for asynchronous input Special flip-flop with very small setup/hold time Doesn’t completely prevent metastabilityclkDQsetup timeviolationmetastablest at eaiaisynchronizera8Metastability One flip-flop doesn’t completely solve problem How about adding more synchronizer flip-flops? Helps, but just decreases probability of metastability So how solve completely? Can’t! May be unsettling to new designers. But we just can’t guarantee a design that won’t ever be metastable. We can just minimize the mean time between failure (MTBF) -- a number often given along with a circuitaisynchronizerslowverylowveryverylowincrediblylowProbabili ty of flip-flop beingmetastable is:9Flip-Flop Set and Reset Inputs Some flip-flops have additional inputs Synchronous reset: clears Q to 0 on next clock edge Synchronous set: sets Q to 1 on next clock edge Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge) Example timing diagram shown Asynchronous set: set Q to 1 immediatelyDQ’QRQ’ARDQQ’ASARDQcycle 1 cycle 2 cycle 3 cycle 4clkDARQ10Initial State of a Controller All our FSMs had initial state But our sequential circuit designs did not Can accomplish using flip-flops with reset/set inputs Shown circuit initializes flip-flops to 01 Designer must ensure reset input is 1 during power up of circuit By electronic circuit designInputs: x;Outputs:bOn2On1On3Of fx=1x=1x=1x=0b’bDQ’ Q’QRSDQSt a t e r e g i s t e rclkresets1 s0n0n1bxCo m b inationallogic11Glitching Glitch: Temporary values on outputs that appear soon after input changes, before stable new output values Design must determine whether glitching outputs may pose a problem If so, may consider adding flip-flops to outputs Delays output by one clock cycle, but may be OK12Active Low Inputs We’ve assume input action occur when input is 1 Some inputs are instead active when input is 0 -- “active low” Shown with inversion bubble So to reset the shown flip-flop, set R=0. Else, keep R=1. DQ’QR13Digital DesignSequential Logic Design: Not really a quiz!! Using the five-step process for designing a controller, convert the following FSM to a controller. Note: You can skip Step