1CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #14 – Placement and RoutingCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.2Register Transfer-Level Design• A register-transfer machine has combinational logic connecting registers:DQCombinationalLogicDQDQCombinationalLogicCombinationalLogicCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.3FPGA Design Flow with TestDesign and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core isport(clock, reset, encr_decr: in std_logic;data_input: in std_logic_vector(31 downto 0);data_output: outstd_logic_vector(31 downto 0);out_full: in std_logic;key_input: in std_logic_vector(31 downto 0);key_read: out std_logic;);end RC5_core;SpecificationVHDLdescriptionFunctional simulationPost-synthesis simulationSynthesizedCircuitCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.4FPGA Design Flow with Test (cont.)ImplementationConfigurationTiming simulationOn chip testingPost-synthesis simulationSynthesizedCircuitCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.5LUT-based Logic Synthesis• Cost metric for static gates is literal• ax + bx’ has four literals, requires 8 transistors• Cost metric for FPGAs is logic element• All functions that fit in an LE have the same costr = q + s’q = g’ + hs = d’d = a + bCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.6Allocation and SchedulingASAPALAP2CprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.7Outline• Recap• Placement and Routing Metrics• FPGA Placement Techniques• Iterative partitioning• Simulated annealing• FPGA Routing TechniquesCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.8Placement and Routing• Two critical phases of layout design:• Placement of components on the chip• Routing of wires between components• Placement and routing interact, but separating layout design into phases helps us understand the problem and find good solutionsCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.9Placement Metrics• Quality metrics for layout:• Area• Delay• Power• Area and delay determined partly by wiring• How do we judge a placement without wiring?• Estimate wire length without actually performing routing• Design time may be important for FPGAsCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.10FPGA Issues• Often want a fast answer• May be willing to accept lower quality result for less place/route time• May be interested in knowing wirability without needing the final configuration• Fast placement: constructive placement, iterative improvement through simulated annealingCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.11Wire Length as a Quality MetricBad Placement Good PlacementCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.12Wire Length Measures• Estimate wire length by distance between components• Possible distance measures:• Euclidean distance (sqrt(x2+ y2))• Manhattan distance (x + y)• Multi-point nets must be broken up into trees for good estimatesEuclideanManhattan3CprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.13Placement• Placement has a set of competing goals• Can’t optimize locally and globally simultaneouslyCD FABE12LUT1 LUT2ABCDE• Use heuristic approaches to evaluate qualityCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.14Placement Techniques• Can construct an initial solution, improve an existing solution• Pairwise interchange is a simple improvement metric:• Interchange a pair, keep the swap if it helps wire length• Some heuristic determines which two components to swapCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.15Placement by Partitioning• Works well for components of fairly uniform size• Partition netlist to minimize total wire length using min-cut criterion• Partitioning may be interpreted as 1-D or 2-D layoutCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.16Recursive PartitioningCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.17Min-Cut Bisecting PartitioningPartition 1 Partition 2ABCD3 nets1 netCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.18Min-Cut Partitioning (cont.)• Swapping A and B:• B drags 1 net• A drags 3 nets• total cut increase: 3 nets• Conclusion: probably not a good swap, but must be compared with other pairs4CprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.19Kernighan-Lin Algorithm• Compute min cut criterion:• Count total net cut change• Algorithm exchanges sets of nodes to perform hill-climbing—finding improvements where no single swap will improve the cut• Recursively subdivide to determine placement detailCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.20Kernighan-Lin Algorithm (cont.)1. Make an initial guess partition into two subsets of equal sizes, and unlock all the vertices in the graph2. Associate a cost D with every vertex i, where D(i) = E(i) – I(i)• I(i) is the number of edges that do not cross the bisection boundary• E(i) is the number of edges that cross the boundary3. Calculate the gain G for all possible swaps between unlocked vertices aiand bi• G(ai,bi) = D(ai) + D(bi) – 2C(ai, bi)• C(ai, bi) is the weight of the edge between (ai,bi) 4. Make the swap for the max G, and lock the nodes5. Iterate until no more swaps can be madeCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.21In-Class Exercise• Step through Kernighan-Lin on the following circuit:V1V0V2V3V4V6V7V5Partition A Partition BCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.22Simulated Annealing• Powerful but CPU-intensive optimization technique• Analogy to annealing of metals:• Temperature determines probability of a component jumping position• Probabilistically accept moves• Start at high temperature, cool to lower temperature to try to reach good placementCprE 583 – Reconfigurable ComputingOctober 5, 2006 Lect-14.23Physical Annealing Analogy• Take a metal and heat to high temperature• Allow it to cool slowly; metal is annealed