1CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #20 – RetimingCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.2Quick Points• HW #4 due Thursday at 12:00pm• Midterm, HW #3 graded by Wednesday• Upcoming deadlines:• November 16 – project status updates• December 5,7 – project final presentations• December 15 – project write-ups dueCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.3Recap – VariablesLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY Numbits ISPORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ;Count : OUT INTEGER RANGE 0 TO 3) ;END Numbits ;CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.4Variables – ExampleARCHITECTURE Behavior OF Numbits ISBEGINPROCESS(X) – count the number of bits in X equal to 1VARIABLE Tmp: INTEGER;BEGINTmp := 0;FOR i IN 1 TO 3 LOOPIF X(i) = ‘1’ THENTmp:= Tmp+ 1;END IF;END LOOP;Count <= Tmp;END PROCESS;END Behavior ;CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.5Variables – Features• Can only be declared within processes and subprograms (functions & procedures)• Initial value can be explicitly specified in the declaration• When assigned take an assigned value immediately• Variable assignments represent the desired behavior, not the structure of the circuit• Should be avoided, or at least used with caution in a synthesizable codeCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.6Variables vs. SignalsLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.all; ENTITY test_delay ISPORT(clk : IN STD_LOGIC;in1, in2 : IN STD_LOGIC;var1_out, var2_out : OUT STD_LOGIC;sig1_out : BUFFER STD_LOGIC;sig2_out : OUT STD_LOGIC);END test_delay;2CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.7Variables vs. Signals (cont.)ARCHITECTURE behavioral OF test_delay ISBEGINPROCESS(clk) ISVARIABLE var1, var2: STD_LOGIC;BEGINif (rising_edge(clk)) THENvar1 := in1 AND in2;var2 := var1;sig1_out <= in1 AND in2;sig2_out <= sig1_out;END IF;var1_out <= var1; var2_out <= var2;END PROCESS;END behavioral;CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.8Simulation ResultCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.9Assert Statements• Assert is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation• Depending on the severity of the problem,the simulator is instructed to continue simulation or halt• Syntax:• ASSERT condition [REPORT “message”][SEVERITY severity_level ];• The message is written when the condition is FALSE• Severity_level can be: Note, Warning, Error (default), or FailureCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.10Array AttributesA’left(N) left bound of index range of dimension N of AA’right(N) right bound of index range of dimension N of AA’low(N) lower bound of index range of dimension N of AA’high(N) upper bound of index range of dimension N of AA’range(N) index range of dimension N of AA’reverse_range(N) index range of dimension N of AA’length(N) length of index range of dimension N of AA’ascending(N) true if index range of dimension N of Ais an ascending range, false otherwiseCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.11Subprograms• Include functions and procedures• Commonly used pieces of code• Can be placed in a library, and then reused and shared among various projects• Use only sequential statements, the same as processes• Example uses:• Abstract operations that are repeatedly performed• Type conversionsCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.12Functions – Basic Features• Always return a single value as a result• Are called using formal and actual parameters the same way as components• Never modify parameters passed to them• Parameters can only be constants (including generics) and signals (including ports);• Variables are not allowed; the default is a CONSTANT• When passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)• Are always used in some expression, and not called on their own3CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.13Function Syntax and ExampleFUNCTION function_name (<parameter_list>)RETURN data_type IS[declarations]BEGIN(sequential statements)END function_name;FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)RETURN BOOLEAN ISBEGIN(sequential statements)END f1;CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.14Procedures – Basic Features• Do not return a value• Are called using formal and actual parameters the same way as components• May modify parameters passed to them• Each parameter must have a mode: IN, OUT, INOUT• Parameters can be constants (including generics), signals (including ports), and variables• The default for inputs (mode in) is a constant, the default for outputs (modes out and inout) is a variable• When passing parameters, range specification should be included (for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)• Procedure calls are statements on their ownCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.15Procedure Syntax and ExamplePROCEDURE procedure_name (<parameter_list>) IS[declarations]BEGIN(sequential statements)END procedure_name;PROCEDURE p1 (a, b: in INTEGER; SIGNAL c: out STD_LOGIC)[declarations]BEGIN(sequential statements)END p1;CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.16Outline• Recap• Retiming• Performance Analysis• Transformations• Optimizations• Covering + RetimingCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.17Problem• Given: clocked circuit• Goal: minimize clock period without changing (observable) behavior• I.e. minimize maximum delay between any pair of registers• Freedom: move placement of internal registersCprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.18Other Goals• Minimize number of registers in circuit• Achieve target cycle time• Minimize number of registers while achieving target cycle time4CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.19Simple ExamplePath Length (L) = 4Can we do better?CprE 583 – Reconfigurable ComputingOctober 31, 2006 Lect-20.20Legal Register Moves• Retiming Lag/LeadCprE 583 – Reconfigurable ComputingOctober 31,