Spartan-II 2.5V FPGA Family: Complete Data SheetIntroduction and Ordering InformationIntroductionFeaturesGeneral OverviewSpartan-II Product AvailabilityOrdering InformationDevice Ordering OptionsDevice Part MarkingRevision HistoryFunctional DescriptionArchitectural DescriptionSpartan-II ArrayInput/Output BlockConfigurable Logic BlockBlock RAMProgrammable Routing MatrixClock DistributionBoundary ScanDevelopment SystemDesign ImplementationDesign VerificationConfigurationConfiguration FileModesSignalsThe ProcessSerial ModesSlave Parallel ModeBoundary-Scan ModeReadbackDesign ConsiderationsUsing Delay-Locked LoopsIntroductionLibrary DLL SymbolsBUFGDLL Pin DescriptionsCLKDLL Primitive Pin DescriptionsDesign FactorsUseful Application ExamplesUsing Block RAM FeaturesOperating ModesBlock RAM CharacteristicsLibrary PrimitivesPort SignalsInverting Control PinsAddress MappingCreating Larger RAM StructuresLocation ConstraintsConflict ResolutionInitializationInitialization in VHDL and SynopsysInitialization in Verilog and SynopsysBlock Memory GenerationUsing Versatile I/OIntroductionFundamentalsOverview of Supported I/O StandardsLibrary SymbolsVersatile I/O PropertiesDesign ConsiderationsTermination ExamplesRevision HistoryDC and Switching CharacteristicsDefinition of TermsDC SpecificationsAbsolute Maximum Ratings(1)Recommended Operating ConditionsDC Characteristics Over Operating ConditionsPower-On RequirementsDC Input and Output LevelsSwitching CharacteristicsGlobal Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)IOB Input Switching Characteristics(1)IOB Input Delay Adjustments for Different StandardsIOB Output Switching CharacteristicsIOB Output Delay Adjustments for Different StandardsCalculation of TIOOP as a Function of CapacitanceDelay Measurement MethodologyConstants for Calculating TIOOPClock Distribution GuidelinesClock Distribution Switching CharacteristicsI/O Standard Global Clock Input AdjustmentsDLL Timing ParametersDLL Clock Tolerance, Jitter, and Phase InformationCLB Switching CharacteristicsCLB Arithmetic Switching CharacteristicsCLB Distributed RAM Switching CharacteristicsCLB Shift Register Switching CharacteristicsBlock RAM Switching CharacteristicsTBUF Switching CharacteristicsJTAG Test Access Port Switching CharacteristicsRevision HistoryPinout TablesPin DefinitionsPinout TablesXC2S15 Device PinoutsAdditional XC2S15 Package PinsXC2S30 Device PinoutsAdditional XC2S30 Package PinsXC2S50 Device PinoutsAdditional XC2S50 Package PinsXC2S100 Device PinoutsAdditional XC2S100 Package PinsXC2S150 Device PinoutsAdditional XC2S150 Package PinsXC2S200 Device PinoutsAdditional XC2S200 Package PinsRevision HistoryDS001 August 2, 2004 www.xilinx.comProduct Specification 1-800-255-7778© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.This document includes all four modules of the Spartan™-II FPGA data sheet.Module 1: Introduction and Ordering InformationDS001-1 (v2.5) August 2, 20046pages• Introduction •Features • General Overview • Product Availability • User I/O Chart • Ordering Information Module 2: Functional DescriptionDS001-2 (v2.2) September 3, 200346 pages• Architectural Description- Spartan-II Array- Input/Output Block- Configurable Logic Block-Block RAM- Clock Distribution: Delay-Locked Loop- Boundary Scan• Development System• Configuration - Configuration Timing• Design ConsiderationsModule 3: DC and Switching CharacteristicsDS001-3 (v2.7) September 3, 200318 pages• DC Specifications - Absolute Maximum Ratings - Recommended Operating Conditions - DC Characteristics- Power-On Requirements- DC Input and Output Levels• Switching Characteristics - Pin-to-Pin Parameters- IOB Switching Characteristics- Clock Distribution Characteristics- DLL Timing Parameters- CLB Switching Characteristics- Block RAM Switching Characteristics- TBUF Switching Characteristics- JTAG Switching CharacteristicsModule 4: Pinout TablesDS001-4 (v2.5) September 3, 200328 pages• Pin Definitions • Pinout Tables IMPORTANT NOTE: The Spartan-II 2.5V FPGA data sheet is created and published in separate modules. This completeversion is provided for easy downloading and searching of the complete document. Page, figure, and table numbers beginat 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easynavigation in this volume.0Spartan-II 2.5V FPGA Family: Complete Data SheetDS001 August 2, 200400Product SpecificationRDS001-1 (v2.5) August 2, 2004 www.xilinx.com 1Product Specification 1-800-255-7778© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThe Spartan™-II 2.5V Field-Programmable Gate Array fam-ily gives users high performance, abundant logic resources,and a rich feature set, all at an exceptionally low price. Thesix-member family offers densities ranging from 15,000 to200,000 system gates, as shown in Ta bl e 1. System perfor-mance is supported up to 200 MHz. Spartan-II devices deliver more gates, I/Os, and featuresper dollar than other FPGAs by combining advanced pro-cess technology with a streamlined Virtex-based architec-ture. Features include block RAM (to 56K bits), distributedRAM (to 75,264 bits), 16 selectable I/O standards, and fourDLLs. Fast, predictable interconnect means that successivedesign iterations continue to meet timing requirements.The Spartan-II family is a superior alternative tomask-programmed ASICs. The FPGA avoids the initial cost,lengthy development cycles, and inherent risk ofconventional ASICs. Also, FPGA programmability permitsdesign upgrades in the field with no hardware replacementnecessary (impossible with ASICs).Features• Second generation ASIC replacement technology- Densities as high as 5,292 logic cells with up to 200,000