DOC PREVIEW
ISU CPRE 583 - Onechip

This preview shows page 1-2-3 out of 10 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

user-friendly OneChip processor will be found in theheart of future commercial products the followingissues must be addressed.• The architectural requirements of OneChip’s coreprocessor should be analyzed in greater detail. Ithas not been studied how much functionality of thefixed part of the OneChip system is actually used.A simpler, more compact core processor than theMIPS-like CPU employed in this work might besufficient.• The presented architecture has yet to beimplemented in custom silicon to overcome thelimitations of the inherently slow TM-1 prototype.• It can be expected that sharing of custom hardwareconstructs across a set of processes will reducehardware resource requirements.• For the application of the OneChip architecture inmultitasking environments some means ofhandling the computational state of severalprocesses sharing one particular PFU must beprovided.• The software environment required for theprogramming and execution of applicationprograms on the OneChip system has yet to bedeveloped. It will be nontrivial.• The design of a run-time operating system thathandles dynamic PFU image compilation andautomated context switching amongst multiplePFU images on a superscalar, time-shared systemwill be challenging.AcknowledgmentsRalph D. Wittig was supported by an NSERCPostgraduate Scholarship and a UofT OpenFellowship. We also acknowledge NSERC and Bell-Northern Research who support the Transmogrifierproject and Xilinx for their ongoing support of FPGAwork at UofT.References[1] J. A. Hennessy, D. L. Patterson, Computer Architecture: AQuantitative Approach, Morgan Kauffmann Publishers, SanMateo, CA, 1990.[2] R. Jeschke, “An FPGA-Based Reconfigurable Coprocessor forthe IBM PC”, M.A.Sc.Thesis, University of Toronto, 1994.[3] P. M. Athanas and H. F. Silverman, “ProcessorReconfiguration Through Instruction-Set Metamorphosis”,Computer, March 1993, pp. 11-18.[4] J. Arnold et al., “The Splash 2 Processor and Applications”,Proceedings International Conference on Computer Design,October 1993.[5] D. Van den Bout et al., “Anyboard: An FPGA-BasedReconfigurable System”, IEEE Design and Test ofComputers, September 1992, pp. 21-30.[6] P. Bertin, D. Roncin, J. Vuillemin, “Introduction toProgrammable Active Memories”, DEC Paris ResearchLaboratory Report #3, 1989.[7] M. Gokhale et al., “SPLASH: A Reconfigurable Linear LogicArray”, Proceedings International Conference on ParallelProcessing, August 1990, pp. 526-532.[8] R. Razdan, M. D. Smith, “A High-PerformanceMicroarchitecture with Hardware-ProgrammableFunctional Units”, Micro 27, November 1994, pp. 172-180.[9] A. DeHon, “DPGA-Coupled Microprocessors: Commodity ICsfor the Early 21st Century”, Proceedings IEEE Workshop onFPGAs for Custom Computing Machines (FCCM’94), April1994.[10] M. J. Wirthlin, B. L. Hutchings, K. L. Gilson, "The NanoProcessor: a Low Resource Reconfigurable Processor",Proceedings IEEE Workshop on FPGAs for CustomComputing Machines (FCCM’94), Napa, CA, April 1994.[11] M. J. Wirthlin, B. L. Hutchings, "A Dynamic Instruction SetComputer", Proceedings IEEE Workshop on FPGAs forCustom Computing Machines (FCCM’95), Napa, CA, April1995.[12] S. Guccione, “List of FPGA-based Computing Machines”,Hyper text link: http://www.io.com/~guccione/HW_list.html[13] M. Bolotski, A. DeHon, T. F. Knight Jr., “Unifying FPGAsand SIMD Arrays”, 2nd International ACM/SIGDAWorkshop on FPGAs (FPGA’94), February 1994.[14] Xilinx Inc., XC6200 FPGA Family, San Jose, CA, 1995.[15] D. Cherepacha, “A Field-Programmable Gate ArraryArchitecture Optimized For Datapaths”, M.A.Sc. Thesis,University of Toronto, 1994.[16] J. Davidson, “FPGA Implementation Of A ReconfigurableMicroprocessor”, Proceedings IEEE Workshop on FPGAs forCustom Computing Machines (FCCM’93), Napa, CA, April1993.[17] P. Chow, The MIPS-X RISC Microprocessor, KluwerAcademic Publishers, MA, 1989.[18] D. Galloway, D. Karchmer, P. Chow, D. Lewis, J. Rose, “TheTransmogifier: The University of Toronto Field-Programmable System”, Second Canadian Workshop onField-Prgrammable Devices, Kingston, ON, June 1994.Available as CSRI Technical Report 306 via anonymous ftpas ftp://ftp.csri.toronto.edu/csri-technical-reports/306/.[19] D. Jones, D. M. Lewis, “A Time-Multiplexed FPGAArchitecture for Logic Emulation”, Proceedings IEEECustom Integrated Circuits Conference (CICC’95), SantaClara, CA, May 1995.[20] Altera Corporation, Data Book, San Jose, CA, 1995.[21] Viewlogic Systems Inc., ViewSynthesis User’s Guide,Marlboro, MA, August 1994.[22] D.R. Coelho, The VHDL Handbook, Kluwer AcademicPublisher, Norwell, MA, 1989.[23] D. A. Patterson, J. L. Hennessy, Computer Organization &Design: The Hardware/Software Interface, MorganKauffman Publishers, San Mateo, CA, 1993.[24] J. Babb, R. Tessier, A. Agarwal, “Virtual Wires: OvercomingPin Limitations in FPGA-based Logic Emulators”,Proceedings IEEE Workshop on FPGAs for CustomComputing Machines (FCCM’93), Napa, CA, April 1993.[25] Motorola, Inc, MC68306 Integrated EC000 Processor User’sManual, Motorola Literature Distribution, Phoenix, AZ,1993.[26] Paul Chow and Rob Jeschke, CMC/University of TorontoRapid-Prototyping Board Users Guide, ICI-068, CanadianMicroelectronics Corporation, 1995.[27] Synopsys Inc, Synopsys Online Documentation V3.1,Mountain View CA, 1993.[28] W. B. Pennebaker, J. L. Mitchell, JPEG Still Image DataCompression Standard, Van Nostrand Reinhold, New York,NJ, 1993.[29] R. B. Lee, “Accelerating Multimedia with EnhancedMicroprocessors”, IEEE Micro, April 1995, pp 22-32.• a two-dimensional DCT that loads or stores onebyte per memory access and performs thetranspose operation using the regular processorregisters (Version III)• a two-dimensional DCT that loads or storesnumerous bytes per memory access (four bytes fora 32-bit system, eight bytes for a 64-bit system)and performs the transpose operation using theregular processor registers (Version IV)• a two-dimensional DCT that loads or storesnumerous bytes per memory access (four bytes fora 32-bit system, eight bytes for a 64-bit system)and performs the transpose operation using thePFU internal registers (Version V)It is expected that improvements in FPGAtechnology in conjunction with the architecturaloptimizations discussed in Section 3.3 will allow theDCT PFU pipeline to be clocked at faster frequenciesthan the lower bound of 1.5 Mhz quoted for theinterconnect limited TM-1 prototype. PFU


View Full Document

ISU CPRE 583 - Onechip

Download Onechip
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Onechip and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Onechip 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?