CprE / ComS 583 Reconfigurable ComputingQuick PointsCeloxica Handel-CFundamentalsVariablesTiming ModelParallelismChannelsSignalsSharing Hardware for ExpressionsBit-width AnalysisArithmetic AnalysisLoop Induction Variable BoundingClamping OptimizationSolving the Linear SequenceFPGA Area SavingsSummarySome Emerging TechnologiesCarbon NanotubesBottom-Up Self-AssemblyNanotubes in Electronics?Possible DevicesDiode LogicPMOS-like Restoring FET LogicProgrammed FET ArraysProgrammable OR-planeSimple Nanowire-Based PLADefect ToleranceResults [Deh05A]Magnetoelectronic DevicesHHE DevicesMagnetoelectronic GatesPower ReducingMagnetoelectronic Look-up TablesSlide 35CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #26 – Course WrapupCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.2Quick Points26SundayDead Week3Finals Week101726Monday41118Lect-2528TuesdayProject Seminars (EDE)1512Electronic Grades Due1929Wednesday613Lect-2630ThursdayProject Seminars (Others)7141Friday8152Saturday9Project Write-ups Deadline16December / November 2006CprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.3Control statements(if, switch, case, etc.)Integer ArithmeticFunctionsPointersBasic types(Structures, Arrays etc.)#define#includeParallelismTimingInterfacesClocksMacro pre-processorRAM/ROMShared expressionCommunicationsHandel-C librariesFP libraryBit manipulationRecursionSide effectsStandard librariesMallocSoftware-only ANSI-C constructsMajority of ANSI-C constructs supported by DKHandel-CAdditions for hardwareCeloxica Handel-C•Handel-C adds constructs to ANSI-C to enable hardware implementation•Synthesizable HW programming language based on C•Implements C algorithm direct to optimized FPGA or RTLCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.4Fundamentals•Language extensions for hardware implementation as part of a system level design methodology•Software libraries needed for verification•Extensions enable optimization of timing and area performance•Systems described in ANSI-C can be implemented in software and hardware using language extensions defined in Handel-C to describe hardware•Extensions focused towards areas of parallelism and communicationCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.5•Handel-C has one basic type - integer•May be signed or unsigned•Can be any width, not limited to 8, 16, 32 etc.Variables are mapped to hardware registersvoid main(void){unsigned 6 a;a=45;}1 0 1 1 0 1 = 0x2da =LSBMSBVariablesCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.6index = 0; // 1 Cyclewhile (index < length){if(table[index] = key)found = index; // 1 Cycleelseindex = index+1; // 1 Cycle}}•Assignments and delay statements take 1 clock cycle•Combinatorial Expressions computed between clock edges•Most complex expression determines clock period•Example: takes 1+n cycles (n is number of iterations)Timing ModelCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.7Parallel Block// 1 Clock Cycle par{a=1;b=2;c=3; }Parallel codepar(i=0;i<10;i++){ array[i]=0;}Parallelism•Handel-C blocks are by default sequential•par{…} executes statements in parallel•Par block completes when all statements complete•Time for block is time for longest statement•Can nest sequential blocks in par blocks•Parallel version takes 1 clock cycle•Allows trade-off between hardware size and performanceCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.8{ … c?b; //read c to b …}{ … c!a+1; //write a+1 to c …}Chan unsigned 6 c;ca bChannels•Allow communication and synchronization between two parallel branches•Semantics based on CSP (used by NASA and US Naval Research Laboratory) •Unbuffered (synchronous) send and receive•Declaration•Specifies data type to be communicatedCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.9•A signal behaves like a wire - takes the value assigned to it but only for that clock cycle•The value can be read back during the same clock cycle•The signal can also be given a default value// Breaking up complex expressionsint 15 a, b;signal <int> sig1;static signal <int> sig2=0; a = 7;par{ sig1 = (a+34)*17;sig2 = (a<<2)+2;b = sig1 + sig2;}SignalsCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.10•Functions provide a means of sharing hardware for expressions•By default, compiler generates separate hardware for each expression •Hardware is idle when control flow is elsewhere in the program•Hardware function body is shared among call sites {…x= x*a + b;y= y*c + d; } int mult_add(int z,c1,c2){ return z*c1 + c2; }{…x= mult_add(x,a,b);y= mult_add(y,c,d); }Sharing Hardware for ExpressionsCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.11•Higher Language Abstraction•Reconfigurable fabrics benefit from specialization•One opportunity is bitwidth optimization•During C to FPGA conversion consider operand widths•Requires checking data dependencies•Must take worst case into account•Opportunity for significant gains for Booleans and loop indices•Focus here is on specializationBit-width AnalysisCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.12•Exampleint a;unsigned b;a = random();b = random(); a = a / 2; b = b >> 4;a = random() & 0xff; a: 32 bits b: 32 bitsa: 31 bits b: 32 bitsa: 31 bits b: 28 bitsArithmetic Analysisa: 8 bits b: 28 bitsCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.13•Applicable to for loop induction variables.•Exampleint i;for (i = 0; i < 6; i++) {…}i: 32 bitsi: 3 bitsi: 3 bitsLoop Induction Variable BoundingCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.14•Multimedia codes often simulate saturating instructions•Exampleint valpredif (valpred > 32767) valpred = 32767else if (valpred < -32768) valpred = -32768valpred: 32 bitsvalpred: 16 bitsClamping OptimizationCprE 583 – Reconfigurable ComputingNovember 30, 2006 Lect-26.15•Sum all the contributions together, and take the data-range union with the initial value•Can easily find conservative range of <0,510>a = 0 <0,0>for i = 1 to 10a = a + 1 <1,460>for j = 1 to 10a = a + 2 <3,480> for k = 1 to 10 a = a + 3 <24,510>...= a + 4 <510,510> Solving the Linear SequenceCprE 583 – Reconfigurable ComputingNovember 30, 2006