1CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #15 – Midterm ReviewCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.2Project Proposals• Group 1 – FPGA Implementation of Frequency-Domain Audio Effects Processor• Five-band equalizer• Frequency shifterCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.3Project Proposals (cont.)• Group 2 – Transparent FPGA-Based Network Analyzer• Layer I pass-through• Layer II passive analyzerCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.4Project Proposals (cont.)• Group 3 – FPGA-Based Library Design for Linear Algebra Applications• Floating-point sparse matrix-vector multiplication• Floating-point banded matrix-vector multiplication• Floating-point lower-upper matrix decompositionCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.5Project Proposals (cont.)• Group 4 – An Improved Approach of Configuration Compression for FPGA-Based Embedded Systems• Improved compression algorithms• LUT-reordering techniquesCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.6Project Proposals (cont.)• Others Projects:• Group 5 – FPGA Ternary Data Conversion• Group 6 – Analysis of Sobel Edge Detection Implementations• Group 7 – Design and Analysis of Artificial Neural Networks on FPGAs• Reminders:• 11/16 – Project Updates (10 minutes)• 12/5-12/7 – Final Presentations (25 minutes)• 12/15 – Final Reports2CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.7$Midterm Review• Using the SiliconPE$PE PEPE PE PEPE PE PEMPPPEMore CachePE$MMXSSEFFT AESCISCSuperscalarPE$VectorPEReconfigurableFabricPEReconfigurable Processor$CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.8Computational Density (Qualitative)• FPGAs can complete more work per unit time than a processor or DSP:• Less instruction overhead• More active computation onto the same silicon area (allows for more parallelism)• Can control operations at the bit level (as opposed to word level)Intel Pentium 4Actel ProASICCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.9Coupling in a Reconfigurable SystemStandalone Processing UnitI/OInterfaceAttached Processing UnitWorkstationMemoryCachesCoprocessorCPUFU• Many places to put reconfigurable computing components• Most implementations involve multiple discrete devices• How should these devices be connected together?CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.10Generic FPGA ArchitectureCLB CLB CLB CLB CLBCLB CLB CLB CLB CLBCLB CLB CLB CLB CLBCLB CLB CLB CLB CLBCLB CLB CLB CLB CLBIOB IOB IOB IOB IOBIOB IOB IOB IOB IOBIOBIOBIOBIOBIOBIOB IOB IOB IOB IOB• Input/Output Buffers (IOBs)• Configurable Logic Blocks (CLBs)• Programmable interconnect meshIsland-style FPGA architecture• FPGA = Field-Programmable Gate ArrayCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.11FPGA Technology• Various FPGA programming technologies (Anti-fuse, (E)EPROM, Flash, SRAM):• SRAM most popularCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.12LUTs and Digital Logic• k inputs Æ 2kpossible input values• k-LUT corresponds to 2kx 1 bit memory• Truth table is stored• 22kpossible functions – O(22k/ k!) uniqueF = A0A1A2 + Ā0A1Ā2 + Ā0 Ā1 Ā20 0 00 0 10 1 00 1 1A0A1A2000001000101002110030010410105011061110700018100190101101101110011121011130111141111151 0 01 0 11 1 01 1 1111101111011001111010101100100011110011010100010110001001000000010102550001.........3CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.13Architectural Issues [AhmRos04A]• What values of N, I, and K minimize the following parameters?• Area• Delay• Area-delay product• Assumptions• All routing wires length 4• Fully populated IMUX• Wiring is half pass transistor, half tri-stateCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.14FPGA Arithmetic• Traditional microprocessors, DSPs, etc. don’t use LUTs• Instead use a w-bit Arithmetic and Logic Unit (ALU)• Carry connections are hard-wired• No switches, no stubs, short wires(1)AND2OR2XOR2(2)ADDSUBCMP3-LUT 3-LUT3-LUT3-LUT(2)ALUABOutOp(1, 2)2-LUTABOut(1)A B CinSumCoutSumCout / CinABCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.15FPGA Arithmetic (cont.)• Hard-wired carry logic supportAltera FLEX 8000 Xilinx XCV4000CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.16Arithmetic (cont.)+X0Y0X1X2X3Z0Y1X0+X1+X2+X3Z1+Y2++++Y3+++Z2• Carry save multiplicationCprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.17LUT-Based Constant Multipliers• Constants can be changed in the LUTs to program new multipliers4-LUTN0–N710101011x NNNNNNNNAAAAAAAAAAAA (N * 1011 (LSN))+ BBBBBBBBBBBB (N * 1010 (MSN))SSSSSSSSSSSSSSSS Product4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT4-LUTN0–N74-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT+S0–S15A0–A11B4–B15CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.18Capacity TrendsYear1985Xilinx Device ComplexityXC200050 MHz1K gatesXC4000100 MHz250K gatesVirtex200 MHz1M gatesVirtex-II 450 MHz8M gatesSpartan80 MHz40K gatesSpartan-II200 MHz200K gatesSpartan-3326 MHz5M gates19911987XC300085 MHz7.5K gatesVirtex-E240 MHz4M gatesXC520050 MHz23K gates1995 1998 1999 2000 2002 2003Virtex-II Pro450 MHz8M gates*2004 2006Virtex-4500 MHz16M gates*Virtex-5550 MHz24M gates*4CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.19Splash 1 ArchitectureF3M3VME BusInterfaceVSB BusControlInterfaceFIFO INFIFO OUTM4F4F11M11M12F12F0M0M7F7F8M8M15F15F1M1M6F6F9M9M14F14F2M2M5F5F10M10M13F13F31M31M24F24F23M23M16F16F28M28M27F27F20M20M19F19F29M29M26F26F21M21M18F18F30M30M25F25F22M22M17F17CprE 583 – Reconfigurable ComputingOctober 10, 2006 Lect-15.20FPGA-based Router• FPX module contains two FPGAs• NID – network interface device• Performs data queuing• RAD – reprogrammable application device• Specialized control sequencesOSC100MHz10 MHzOSCSDRAM(backside)8Mbit ZBTSRAM8Mbit ZBTSRAMDeviceInterfaceNetworkNIDRADReprogrammableApplicationDeviceVirtex1000E fg680RAD/NID StatusSDRAM(backside)SRAMProgramRADReprogOC3 / OC12 / OC48 Linecard ConnectorEPROMNID62.5 MHzVRM: 1.8V SwitcherJTAGWUGS Switch Backplane ConnectorFPXWashU / ARLJuly, 2000JL / MROSCCprE 583 –