1CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #19 –VHDL for Synthesis IICprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.2Recap – Moore FSM Example• Moore FSM that recognizes sequence “10”S0 / 0 S1 / 0 S2 / 1000111resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observedS2: “10”observedCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.3Recap – Mealy FSM Example• Mealy FSM that recognizes sequence “10”S0 S10 / 01 / 0 1 / 00 / 1resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observedCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.4Moore FSM Example – VHDLTYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;U_Moore: PROCESS (clock, reset)BEGINIF(reset = ‘1’) THENMoore_state <= S0;ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state ISWHEN S0 =>IF input = ‘1’ THENMoore_state <= S1; ELSEMoore_state <= S0;END IF;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.5Moore FSM Example – VHDL (cont.)WHEN S1 =>IF input = ‘0’ THEN Moore_state <= S2; ELSEMoore_state <= S1; END IF;WHEN S2 =>IF input = ‘0’ THENMoore_state <= S0; ELSE Moore_state <= S1; END IF;END CASE;END IF;END PROCESS;Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.6Mealy FSM Example – VHDLTYPE state IS (S0, S1);SIGNAL Mealy_state: state;U_Mealy: PROCESS(clock, reset)BEGINIF(reset = ‘1’) THENMealy_state <= S0;ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state ISWHEN S0 =>IF input = ‘1’ THEN Mealy_state <= S1; ELSEMealy_state <= S0;END IF;2CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.7Mealy FSM Example – VHDL (cont.)WHEN S1 =>IF input = ‘0’ THENMealy_state <= S0; ELSEMealy_state <= S1;END IF;END CASE;END IF;END PROCESS;Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.8Finite State Machine Design• A more “fair” bus arbiter• 5 resources contending for the bus• Inputs r1 -> r5, Outputs g1 -> g5• Tuesday’s arbiter• Resource r(i) has precedence over r(j>i) when bus is idle• Once granted access, resources can hold on to the bus as long as they want to• Group 1 – same precedence, but now resource r(i) can only have bus for i cycles at a time• Group 2 – if multiple requests for bus, tie goes to least recently used resource• Group 3 – each resource can also “interrupt” the bus if necessary and gain instant accessIdle000 1xx Reset gnt1 g 1 ⁄1 = x1x gnt2 g 2 ⁄1 = xx1 gnt3 g 3 ⁄1 = 0xx 1xx 01x x0x 001xx0 CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.9Outline• Recap• Memories• Modeling RAM• Modeling ROM• Writing Synthesizable Code• Additional VHDL Features• Functions• Procedures• Attributes• Variables• ConstantsCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.10Generic RAMLIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY ram ISGENERIC (bits: INTEGER:=8; -- # of bits per wordwords: INTEGER := 16); -- # of words in the memoryPORT (wr_ena, clk: IN STD_LOGIC;addr: IN INTEGER RANGE 0 to words-1;data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0);data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0));END ram; CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.11Generic RAM (cont.)ARCHITECTURE behavioral OF ram ISTYPE vector_array IS ARRAY (0 TO words-1) OFSTD_LOGIC_VECTOR(bits – 1 DOWNTO 0);SIGNAL memory: vector array;BEGINPROCESS(clk)BEGINIF(wr_ena=‘1’) THENIF (clk’EVENT AND clk=‘1’) THENmemory(addr) <= data_in;END_IF;END IF;END PROCESS;data_out <= memory(addr);END ram;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.12Generic ROMLIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY rom ISGENERIC (bits: INTEGER:=8; -- # of bits per wordwords: INTEGER := 8); -- # of words in the memoryPORT ( addr: IN INTEGER RANGE 0 to words-1;data: OUT STD_LOGIC_VECTOR(bits – 1 downto 0));END rom;3CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.13Syntax:CONSTANT name : type := value;Examples:CONSTANT high : STD_LOGIC := ‘1’;CONSTANT datamemory : memory := ((X"00", X"02");ConstantsCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.14• Constants can be declared in a PACKAGE, ENTITY, or ARCHITECTURE• When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities• When declared in an ARCHITECTURE, theconstant is local, i.e., it is visible only within this architecture• When declared in an ENTITY, the constant can be used in all architectures associated with this entityConstants – FeaturesCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.15Generic ROM (cont.)ARCHITECTURE behavioral OF rom ISTYPE vector_array IS ARRAY (0 TO words-1) OFSTD_LOGIC_VECTOR(bits – 1 DOWNTO 0);CONSTANT memory: vector_array :=("0000_0000","0000_0010","0000_0100","0000_1000","0001_0000","0010_0000","0100_0000","1000_0000");BEGINdata <= memory(addr);END rom;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.16RAM16X1SODWEWCLKA0A1A2A3RAM32X1SODWEWCLKA0A1A2A3A4RAM16X2SO1D0WEWCLKA0A1A2A3D1O0==LUTLUTorLUTRAM16X1DSPODWEWCLKA0A1A2A3DPRA0 DPODPRA1DPRA2DPRA3orDistributed RAM• CLB LUT configurable as Distributed RAM• A LUT equals 16x1 RAM• Implements Single and Dual-Ports• Cascade LUTs to increase RAM size•Synchronous write• Synchronous/Asynchronous read• Accompanying flip-flops used for synchronous readCprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.17RAM 16x1library IEEE;use IEEE.STD_LOGIC_1164.all;library UNISIM;use UNISIM.all;entity RAM_16X1_DISTRIBUTED isport(CLK : in STD_LOGIC;WE : in STD_LOGIC;ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC;DATA_OUT : out STD_LOGIC);end RAM_16X1_DISTRIBUTED;CprE 583 – Reconfigurable ComputingOctober 26, 2006 Lect-19.18RAM 16x1 (cont.)architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is-- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string;attribute INIT of