SX Family FPGAsLeading Edge PerformanceSpecificationsFeaturesOrdering InformationPlastic Device ResourcesSX Family FPGAsGeneral DescriptionSX Family ArchitectureProgrammable Interconnect ElementOther Architectural FeaturesDedicated Test ModeProgramming3.3 V / 5 V Operating ConditionsPCI Compliance for the SX FamilyA54SX16P AC Specifications for (PCI Operation)A54SX16P DC Specifications (3.3 V PCI Operation)A54SX16P AC Specifications (3.3 V PCI Operation)Power-Up SequencingPower-Down SequencingEvaluating Power in SX DevicesEstimating Power ConsumptionGuidelines for Calculating Power ConsumptionSample Power CalculationJunction Temperature (TJ)SX Timing ModelRegister Cell Timing CharacteristicsTiming CharacteristicsCritical Nets and Typical NetsLong TracksTiming DeratingA54SX08 Timing CharacteristicsA54SX16 Timing CharacteristicsA54SX16P Timing CharacteristicsA54SX32 Timing CharacteristicsPin DescriptionPackage Pin Assignments84-Pin PLCC208-Pin PQFP144-Pin TQFP176-Pin TQFP100-Pin VQFP313-Pin PBGA329-Pin PBGA144-Pin FBGADatasheet InformationList of ChangesDatasheet CategoriesProduct BriefAdvancedUnmarked (production)Datasheet SupplementInternational Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR)June 2006 i© 2006 Actel Corporation See the Actel website for the latest version of the datasheet.SX Family FPGAsLeading Edge Performance• 320 MHz Internal Performance• 3.7 ns Clock-to-Out (Pin-to-Pin)• 0.1 ns Input Setup• 0.25 ns Clock SkewSpecifications• 12,000 to 48,000 System Gates• Up to 249 User-Programmable I/O Pins• Up to 1,080 Flip-Flops• 0.35 µ CMOSFeatures• 66 MHz PCI• CPLD and FPGA Integration• Single-Chip Solution• 100% Resource Utilization with 100% Pin Locking• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance• Very Low Power Consumption• Deterministic, User-Controllable Timing• Unique In-System Diagnostic and Debug Capabilitywith Silicon Explorer II• Boundary Scan Testing in Compliance with IEEEStandard 1149.1 (JTAG)• Secure Programming Technology Prevents ReverseEngineering and Design Theft™euSX Product ProfileDevice A54SX08 A54SX16 A54SX16P A54SX32CapacityTypical GatesSystem Gates8,00012,00016,00024,00016,00024,00032,00048,000Logic ModulesCombinatorial Cells7685121,4529241,4529242,8801,800Register Cells (Dedicated Flip-Flops) 256 528 528 1,080Maximum User I/Os 130 175 175 249Clocks 3333JTAG Yes Yes Yes YesPCI ––Yes–Clock-to-Out 3.7 ns 3.9 ns 4.4 ns 4.6 nsInput Setup (external) 0.8 ns 0.5 ns 0.5 ns 0.1 nsSpeed Grades Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3Temperature Grades C, I, M C, I, M C, I, M C, I, MPackages (by pin count)PLCCPQFPVQFPTQFPPBGAFBGA84208100144, 176–144–208100176–––208100144, 176–––208–144, 176313, 329–v3.2SX Family FPGAsii v3.2Ordering Information Plastic Device Resources Part Number A54SX08 = 12,000 System Gates A54SX16 = 24,000 System Gates A54SX16P = 24,000 System Gates A54SX32 = 48,000 System GatesSpeed Grade Blank = Standard Speed –1 = Approximately 15% Faster than Standard –2 = Approximately 25% Faster than Standard –3 = Approximately 35% Faster than StandardPackage Type BG = Ball Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack FG = Fine Pitch Ball Grid Array (1.0 mm)Package Lead CountApplication (Temperature Range) Blank = Commercial (0 to +70˚C) I = Industrial (–40 to +85˚C) M = Military (–55 to +125˚C) PP = Pre-productionA54SX16P2PQ208Blank = Not PCI Compliant P = PCI CompliantGLead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging–Device User I/Os (including clock buffers)PLCC 84-PinVQFP100-PinPQFP208-PinTQFP144-PinTQFP176-PinPBGA 313-PinPBGA 329-PinFBGA 144-PinA54SX08 69 81 130 113 128 – – 111A54SX16 – 81 175 – 147 – – –A54SX16P – 81 175 113 147 – – –A54SX32 – – 174 113 147 249 249 –Note: Package Definitions (Consult your local Actel sales representative for product availability):PLCC = Plastic Leaded Chip CarrierPQFP = Plastic Quad Flat PackTQFP = Thin Quad Flat PackVQFP = Very Thin Quad Flat PackPBGA = Plastic Ball Grid ArrayFBGA = Fine Pitch (1.0 mm) Ball Grid Arrayv3.2 iiiTable of ContentsSX Family FPGAsSX Family FPGAsGeneral Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1SX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73.3 V / 5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7PCI Compliance for the SX Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9A54SX16P AC Specifications for (PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10A54SX16P DC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-12A54SX16P AC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-13Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15Power-Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15Evaluating Power in SX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16SX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23Package Pin Assignments84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1208-Pin PQFP . . . . . . . …