1CprE / ComS 583Reconfigurable ComputingProf. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State UniversityLecture #17 – Introduction to VHDL IICprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.2Quick Points• Midterm course evaluation form available on WebCT• HW #4 – VHDL for synthesis• Due Thursday, November 2 (12:00pm)• Work with your project groupCprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.3Recap – PROCESS Block• List of signals to which the process is sensitive• Whenever there is an event on any of the signals in the sensitivity list, the process fires• Every time the process fires, it will run in its entirety• WAIT statements are NOT allowed in a processes with sensitivity listlabel: process (sensitivity list)declaration part beginstatement partend process;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.4Processes in VHDL• Processes describe sequential behavior• Processes in VHDL are very powerful statements• Allow to define an arbitrary behavior that may be difficult to represent by a real circuit• Not every process can be synthesized• Use processes with caution in the code to be synthesized• Use processes freely in testbenchesCprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.5Mixed Style ModelingProcessPortsininoutoutinoutComponentComponentSignalDataflow ExpressionX <= (Y = ‘1’) and (Z = “110”)Process (clk)if clk’Event andclk=‘1’ thenCount <= Count + 1;end if;end process;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.6Design Exercise• Create the entity declaration for some component of your final project• Names, ports, signal types• Just the structureENTITY entity_name ISPORT (port_name : signal_mode signal_type;port_name : signal_mode signal_type;………….port_name : signal_mode signal_type);END entity_name;2CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.7Outline• Recap• Dataflow Style• Logic Gates• Decoders / Encoders• Arithmetic Functions• A Structural Example• Behavioral Style• Registers• CountersCprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.8Dataflow VHDL• All concurrent statements• Major instructions:• Concurrent signal assignment (⇐)• Conditional concurrent signal assignment (when-else)• Selected concurrent signal assignment (with-select-when)• Generate scheme for equations (for-generate)CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.9Dataflow Example – Full AdderENTITY fulladd ISPORT ( x : IN STD_LOGIC ;y : IN STD_LOGIC ; cin : IN STD_LOGIC ;s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ;END fulladd ;ARCHITECTURE dataflow OF fulladd ISBEGINs <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;END dataflow ;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.10Logical Operators• AND, OR, NAND, NOR, XOR, NOT, XNOR• Only NOT has order of precedence• Otherwise, no implied precedence• Example: y = ab + cd• y <= a AND b or c AND d; -- Equivalent to• y <= ((a AND b) OR c) AND d ; -- Equivalent to• y = (ab + c)dCprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.11Arithmetic Operators• For basic arithmetic operators on std_logictypes, use the IEEE libraries• Standard addition, subtraction, multiplicationLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- or std_logic_signed.allsignal A : STD_LOGIC_VECTOR(3 downto 0);signal B : STD_LOGIC_VECTOR(3 downto 0);signal C : STD_LOGIC_VECTOR(3 downto 0);……C <= A + B;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.1216-bit AdditionLIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;END adder16 ;ARCHITECTURE Dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;END Dataflow ;3CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.13Conditional Signal Assignmenttarget_signal <= value1 when condition1 elsevalue2 when condition2 else. . .valueN-1 when conditionN-1 elsevalueN;When - Else.…Value NValue N-1Condition N-1Condition 2Condition 1Value 2Value 1Target Signal…010101CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.142:1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux2to1 ISPORT (w0, w1, s : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;END mux2to1 ;ARCHITECTURE dataflow OF mux2to1 ISBEGINf <= w0 WHEN s = '0' ELSE w1 ;END dataflow ;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.15Priority EncoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY priority ISPORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;END priority ;ARCHITECTURE dataflow OF priority ISBEGINy <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;z <= '0' WHEN w = "0000" ELSE '1' ;END dataflow ;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.16choices_1choices_2choices_Nexpression1expression2expressionNtarget_signalwith choice_expression selecttarget_signal <= expression1 when choices_1,expression2 when choices_2,. . .expressionN when choices_N;With –Select-Whenchoice expressionSelected Signal AssignmentCprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.174:1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux4to1 ISPORT (w0, w1, w2, w3 : IN STD_LOGIC ;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;END mux4to1 ;ARCHITECTURE dataflow OF mux4to1 ISBEGINWITH s SELECTf <= w0 WHEN "00",w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;END dataflow ;CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.18Generate Statements• A way to simplify a pattern of concurrent statements• Can’t do regular FOR…LOOP in dataflowFor - Generatelabel: FOR identifier IN range GENERATEBEGIN{Concurrent Statements}END GENERATE;4CprE 583 – Reconfigurable ComputingOctober 18, 2006 Lect-17.19Parity Examplexor_out(1)xor_out(2)xor_out(3)xor_out(4)xor_out(5)xor_out(6)xor_out(7)xor_out(0)ARCHITECTURE parity_dataflow OF parity ISSIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);BEGINxor_out(0) <= parity_in(0);G2: FOR i IN 0 TO 6 GENERATExor_out(i+1) <= xor_out(i) XOR parity_in(i+1);end generate G2;