1CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghState ElementsRS latchR,S control mode (reset, set, storage)Q,Q’ track R and SR=1, S=1 invalidD latchC controls mode (0=latched, 1=transparent)D is data input (“copied” during transparent)Signal value triggered: Q,Q’ track D when C=1Guarantees R=1,S=1 can not be doneD flip-flop (falling or negative edge triggered)Two cascaded D latchesC=1 means 1stlatch transparent, 2ndlatchedC=0 means 1stlatch latched, 2ndtransparentOutput changes on falling edge (C: 1=>0) D flip-flop (rising or positive edge triggered)Same as falling edge triggeredOutput changes on rising edge (C: 0=>1)CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghSignaling BehaviorRS latch behaviorQ goes low R=1,S=0Storage modeQ goes high R=0,S=12CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghSignaling BehaviorD latch behaviorQ goes C=1, D=1Q tracked D when C=1Q went low C=1,D=0Q stays low b/c C=0CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghSignaling BehaviorD flip-flop (falling edge triggered)no change b/c not falling edgetracks D at time of falling edgeno change b/c not a falling edge3CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghSignaling BehaviorRS latch behaviorD latch behaviorD flip-flop (falling edge triggered)CS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh57Example circuits and clocking Suppose we want to:• 1-bit value A stored in a D flip-flop• 1-bit value B stored in a D flip-flop• 1-bit value C stored in a D flip-flip• Do addition of A and B, producing C C = A + B• What is the circuit?• Need three D flip-flops• Need one 1 bit adder4CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghExample circuits and clockingCS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh59Example circuits and clocking Is there any difference in the delay with this one? In fact, sequential logic often looks like this….5CS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh60Example circuits and clocking Now, suppose we want to build a 4-bit counter?• Counter increments by 1 for a clock pulse (falling edge event)• 4 1-bit adders• 4 1-bit D flip-flops What’s the circuit? How often to “pulse” the clock (increment counter)?CS/CoE1541: Intro. to Computer ArchitectureUniversity of PittsburghExample circuits and clockingRecall: The flip-flops are edge triggered -- assuming falling edge (negative)How often can an edge event happen?No more frequent than the maximum propagation delayLet’s compute the delay -- assume 2ns for latch to stabilize and 4ns for adder6CS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh62Example circuits and clocking Values of output bits must all be stable• I.e., can’t pulse the clock (increment) until all four bits are computed Adder circuit is ripple-carry: Must wait for carries• 4ns per adder• 4-bit adder• thus, 4 * 4ns = 16ns for the adder Flip-flops• Must wait for 1stlatch of last bit to stabilize (others done in parallel)• Must wait for 2ndlatch of all bits to stabilize (all done in parallel)• thus, 2ns + 2ns = 4ns Overall delay = 16ns + 4ns = 20ns. Clock pulse is 20ns. CS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh63Example circuits and clockingClock pulse is 20nsFlip-flops are falling edge triggeredThus, a clock falling edge every 20ns7CS/CoE1541: Intro. to Computer ArchitectureUniversity of Pittsburgh64Example circuits and clockingCan we build a counter with just flip-flops?What’s the maximum clock pulse
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