CS/COE0447 Computer Organization & Assembly LanguageTopicsExample: LUI, ANDI and ORIDocumentation [greencard]: LUI, ANDI, ORIShift InstructionsSlide 6Example of ShiftsPuzzle: How we do we load a 32 bit immediate value into a register using core IS?Puzzle: How we do we load a 32 bit immediate value into a register?Puzzle: how will we fit a 32-bit immediate value into an instruction?Loading 32-bit immediate value into registersLoading addresses into registersQuick ExerciseQuick Exercise AnswerAddresses Specify Byte LocationsMemory Transfer InstructionsByte OrderingSlide 18Procedure ExampleControlImplementing a for-loopSlide 22Slide 23If Statement ExampleIf Then Else ExampleSlide 26Slide 27Instruction Format for BranchesSlide 29Instruction Format for JumpsSlide 311CS/COE0447Computer Organization & Assembly LanguageChapter 2 Part 22Topics •More types of instructions–Translation into machine code–How they work (execution)–Understanding the technical documentation (green card)•Immediate values–Sign and Zero extension of immediates–Loading large immediate values into registers, which leads us to pseudo instructions (source versus basic in MARS)•Addressing: bytes, half-words, words, and alignment Ask any remaining questions from Lab 2•Algorithms in assembly language: arrays, loops, if-statements (presented through example code). Ask remaining questions from Lab 3•Assembly and execution of branch and jump instructions3Example: LUI, ANDI and ORI lui $t1, 0x7F40 # load 0x7F400000 into $t1 #lui is load upper immediate #upper: upper 2 bytes (4 hex digits; 16 bits) #immediate: part of the instruction addi $t2, $t1, 0x777 andi $t3, $t2, 0x5555 # bitwise and ori $t4,$t2,0x5555 # bitwise or Trace in lecture4Documentation [greencard]: LUI, ANDI, ORIlui I R[rt] = {imm,16’b0} f_hexandi I R[rt] = R[rs] & ZeroExtImm (3) c_hexori I R[rt] = R[rs] | ZeroExtImm (3) d_hex(3) ZeroExtImm = {16{1’b0},immediate}In Verilog: In lecture: machine code understand the green card info above 16‘b1 // 16 bits, with binary value 11’b0 // 1 bit, which is 0{a,b} // ab3{a} // aaa{3{a},b} // aaab5Shift Instructions•Bit-wise logic operations •<op> <rdestination> <rsource> <shamt>•Examples–sll $t0, $s0, 4 # $t0 = $s0 << 4–srl $s0, $t0, 2 # $s0 = $t0 >> 2•These are the only shift instructions in the core instruction set•Green card is wrong for sll and srl; “rs” should be “rt”Name Fields CommentsR-format opNOTUSEDrt rd shamt funct shamt is “shift amount”6Shift Instructions•Variations in the MIPS-32 instruction set:–Shift amount can be in a register (“shamt” field not used) •sllv, srlv, srav –Shift right arithmetic (SRA) keeps the sign of a number•sra $s0, $t0, 4 •Pseudo instructions:–Rotate right/left: ror, rol•The point: lots of possible variations in shift instructions. Whether they are in the core ISA depends on the assembly language. [MIPS, being RISC, has only a couple in the core]7 .text li $t0,0x77 li $t2,3 sll $t0,$t0,3 srl $t2,$t2,2 Example of Shifts$t0 = 0000 0000 0000 0000 0000 0000 0111 0111$t2 = 0000 0000 0000 0000 0000 0000 0000 0011So, $t0 becomes 0x000003b8 $t2 becomes 0x00000000000008Puzzle: How we do we load a 32 bit immediate value into a register using core IS? •Suppose we want to load 0x76B52134 into $t0•What instruction will do this?•lw? Nope: lw loads a value from memory, e.g., –lw $t0,4($t2) loads the word at M[4+$t2] into $t0•lbu? Nope: lbu also loads a value from memory, e.g.,–lbu $t0,4($t2) loads the byte at M[4+$t2] padded to left with 26 0s•lhu? Nope: lhu also loads a value from memory, e.g., –lhu $t0,4($t2) loads the 16 bits at M[4+$t2] padded to left with 16 0s •lui? Nope: –lui $t0,0x7F40 loads a 16-bit immediate value followed by 16 0s•That’s all the load instructions in the core instruction set!9Puzzle: How we do we load a 32 bit immediate value into a register?•Let’s try defining an instruction:• li $t0, 0x76B52134•We need to choose an instruction format–R: op (6) rs (5) rt (5) rd (5) shmt (5) funct(6)–I: op(6), rs (5), rt (5), imm (16)–J: op(6), address (26)•MIPS: a key design decision is that all instructions are 32 bits. This is not true for many other ISAs•How will we fit a 32-bit immediate value into an instruction?10Puzzle: how will we fit a 32-bit immediate value into an instruction?•We can’t! Recall, we want: 0x76b52134  $t0•li $t0,0x76b52134 is translated into 2 instructions [“li” is a pseudo instruction; not implemented in the hardware]•lui $at, 0x76b5•ori $t0, $at, 0x2134•There’s a tradeoff between simplicity of instructions and the number of instructions needed to do something•MIPS is RISC: reduced instruction set computer0010000100110100$t00111011010110101 0000000000000000$at011101101011010111Loading 32-bit immediate value into registers •Recall, we want: 0x76b52134  $t0 Basic Source lui $1, 30389 li $t0, 0x76b52134 ori $8, $1, 8500 In Mars.jar, after you assemble the code12Loading addresses into registers •.data places values in memory starting at 0x10010000. So, 32 bits are needed to specify memory addresses.•1 instruction is impossible: the address would take up the entire instruction! •Use another pseudo instruction called la Basic Source lui $1, 4097 la $t0, 0x10010008 ori $8, $1, 8 In Mars.jar, after you assemble the code13Quick Exercise•From A-57 (in the appendix): load immediate li rdest, imm e.g., li $t0,0xffffffff “Move the immediate imm into register rdest”•What type of instruction is this? E.g., is this an R-format instruction? Perhaps an I-format one? … Please explain.14Quick Exercise Answer•“li” is a pseudo instruction. The instruction is translated by the assembler into two instructions in the actual machine code that is executed by the computer.•We saw an example on slide 1115Addresses Specify Byte Locations–Addresses are aligned: addresses are multiples of X, where X is the number of bytes. [practice in next lab]–word (4 bytes) addresses are multiples of 4; half-word (2 bytes) addresses are multiples of 2–In lecture: what this looks like in Mars.0000000100020003000400050006000700080009000A000B32-bitWordsBytes Addr.000C000D000E000FHalfWordsAddr =??Addr =??Addr =??Addr