CS/COE0447 Computer Organization & Assembly LanguageContinuing from Chapter 2 Part 1But first: errors on green card p1.ANDI and ORILong Immediates (e.g., memory addresses!)Loading a memory addressA programSlide 8Quick ExerciseQuick Exercise AnswerMemory Transfer InstructionsMachine Code ExampleMemory ViewSlide 14Example of Memory AllocationByte OrderingByte Ordering ExampleMemory OrganizationMisalignment ExampleShift InstructionsSlide 21Slide 22ControlControl, cont’dSlide 25Slide 26Slide 27Instruction FormatSlide 29Instruction Format, cont’dMIPS Addressing ModesSummary1CS/COE0447Computer Organization & Assembly LanguageChapter 2 Part 22Continuing from Chapter 2 Part 1Starts with modified versions of Part 1’s last 5 slides3But first: errors on green card p1.•lbu I 0/24hex  lbu I 24hex•lhu I 0/25hex  lbu I 25hex•lw I 0/23hex  lw I 23hex•EG: machine code for lbu $8,2($7)•sll and srl: replace “rs” with “rt” (example later)4ANDI and ORIlui I R[rt] = {immediate,16’b0}andi I R[rt] & ZeroExtImm (3)(3) ZeroExtImm = {16{1’b0},immediate}In Verilog: 16'h704f // a 16-bit hex number1’b0 // a 1-bit binary number lui $t1, 0x7F40 addi $t2, $t1, 0x777 andi $t3, $t2, 0x5555 Above and ori version in lecture5Long Immediates (e.g., memory addresses!) •Sometimes we need a long immediate, e.g., 32 bits•MIPS requires that we use two instructions–lui $t0, 0xaa55–ori $t0, $t0, 0xcc33–Note: this wouldn’t work if ori used SignExtImm rather than ZeroExtImm! (“or” with 0 == copy; like adding 0 in arithmetic)1010101001010101 1100110000110011$t01010101001010101 0000000000000000$t06Loading a memory address •.data places values in memory starting at 0x10010000. 32 bits are needed to specify memory addresses.•1 instruction is impossible: the address would take up the entire instruction!! (no room for the opcode!!)•la $t0, 0x1001008 is a pseudo instruction – not implemented in the hardware lui $1, 4097 la $t0, 0x10010008 ori $8, $1, 8 lw $t1, 0($t0) #look at green card to #understand this addr mode7A program•Get sample1.asm from the schedule•Load it into the simulator•Figure out the memory contents, labels•Trace through the code8 .data # sample1.asma: .word 3,4c: .word 5,6 .text la $t0,c # address of c la $t1,k # address of k lw $s0,0($t0) # load c[0] lw $s1,4($t1) # load k[1] slt $s3,$s0,$s1 # if c[0] < k[1], $s3 = 1, else $s3 = 0 beq $s3,$0,notless # if c[0] < k[1] swap their values sw $s0,4($t1) sw $s1,0($t0)notless: .datak: .word 0xf,0x11,0x129Quick Exercise•From A-57:•load immediate• li rdest, imm e.g., li $t0,0xffffffff•“Move the immediate imm into register rdest”•[nothing is said about sign or 0 extension]•What type of instruction is this? E.g., is this an R-format instruction? Perhaps an I-format one? … Please explain.10Quick Exercise Answer•In class11Memory Transfer Instructions•To load/store a word from/to memory:–LOAD: move data from memory to register•lw $t3, 4($t2) # $t3  M[$t2 + 4]–STORE: move data from register to memory•sw $t4, 16($t1) # M[$t1 + 16]  $t4•Support for other data types than 32-bit word is needed–16-bit half-word•“short” type in C•16-bit processing is common in signal processing• lhu and sh in MIPS–8-bit byte•“char” type in C•8-bit processing is common in controller applications•lbu and sb12Machine Code Exampleswap:sll $t0, $a1, 2add $t1, $a0, $t0lw $t3, 0($t1)lw $t4, 4($t1)sw $t4, 0($t1)sw $t3, 4($t1)jr $ravoid swap(int v[], int k){int temp;temp = v[k];v[k] = v[k+1];v[k+1] = temp;}$a0: pointer to array$a1: k13Memory View•Viewed as a large, single-dimensional 8-bit array with an address (“byte address”)•A memory address is an index into the arrayBYTEBYTEBYTEBYTEBYTEBYTE543210…14•Addresses Specify Byte Locations–Address of first byte –Addresses are aligned: addresses are multiples of X, where X is the number of bytes.–word (4 bytes) addresses are multiples of 4; half-word (2 bytes) addresses are multiples of 20000000100020003000400050006000700080009000A000B32-bitWordsBytes Addr.000C000D000E000FHalfWordsAddr =??Addr =??Addr =??Addr =??000000040008000C00020000000400060008000A000C000EIn Class: match up with format of memory shown by simulator15Example of Memory Allocation .data b2: .byte 2,3,4 .align 2 .word 5,6,7 .text la $t0,b2 lbu $t2,0($t0) # $t2 = 0x02 lbu $t2,1($t0) # $t2 = 0x03 lbu $t2,3($t0) # $t2 = 0x00 (nothing was stored there) lbu $t2,4($t0) # $t2 = 0x00 (top byte of the 5 word) lbu $t2,7($t0) # $t2 = 0x05 (bottom byte of the 5 word)16Byte Ordering•How should bytes within multi-byte words be ordered in memory?•Conventions–“Big Endian” machines (including MIPS machines)•Least significant byte has highest address.data.word 3 (0x00000003; 03 is the least sig. byte)03 is in 10010003–“Little Endian” machines•Least significant byte has lowest address•03 would be in 1001000017Byte Ordering Example•Big Endian–Least significant byte has highest address•Little Endian–Least significant byte has lowest address•Example–Suppose variable x has 4-byte representation 0x01234567–Suppose address of x is 0x1000x100 0x101 0x102 0x10301 23 45 670x100 0x101 0x102 0x10367 45 23 01Big EndianLittle Endian01 23 45 6767 45 23 0118Memory Organization•232 bytes with byte addresses from 0 to 232 – 1•230 words with byte addresses 0, 4, 8, …, 232 – 4 •231 half-words with byte addresses 0, 4, 8, …, 232 – 2–Suppose addresses were 5 bits. •Bytes: 0…31; •Words: 0,4,8,12,14,16,20,24,28, i.e., 0,4,..,2^5 – 4; •Half-words: 0,2,4,…, 28, 30, i.e., 0,2,…,2^5-2.WORDWORDWORDWORDWORDWORD201612840…Unsigned numbers in n bits: 0 to 2^n - 1Eg: 3 bits: 0 to 7 4 bits: 0 to 15 5 bits: 0 to 3119Misalignment Example•Misaligned accesses (errors!)–lw $t1, 3($zero)–lbu $t1, 1($zero)•Alignment issue does not exist for byte accesses…0 1 2 311109804 7654820Shift Instructions•Bit-wise logic operations •<op> <rdestination> <rsource> <shamt>•Examples–sll $t0, $s0, 4 # $t0 = $s0 << 4–srl $s0, $t0, 2 # $s0 = $t0 >> 2•These are the only shift instructions in the core instruction set•Green card is wrong for sll and srl; “rs” should be “rt”Name Fields CommentsR-format opNOTUSEDrt rd shamt funct shamt