CS/COE0447 Computer Organization & Assembly LanguageSlide 2Control UnitExamplesInstruction Execution (reminder)Slide 7Control Signal TableSlide 9Slide 10ALU ControlSlide 12ALU ControlALU Control Unit Truth TableSlide 15Control Unit DesignSlide 17Slide 18Datapath w/ JumpTransition to Multi-Cycle ControlWhat We Have NowFunctional Units UsedSingle-Cycle Execution TimingSingle-Cycle Exe. ProblemA Multi-cycle DatapathMulti-cycle Approach1CS/COE0447Computer Organization & Assembly LanguageChapter 4 Part 223Control Unit•Implements (in hardware) an if statement:–If opcode == 000000 # r-type instruction•MemWrite = 0 •MemRead = 0•MemToReg = 0•… # values assigned for all the control unit’s output signals–Elif opcode == 0x23 # lw•MemWrite = 0•MemRead = 1•MemToReg = 1•…–Elif opcode == 0x4 # beq•MemWrite = 0•MemRead = 0•MemToReg = X # don’t care•…–… # an Elif test for each opcode4Examples•In Lab, you did examples for an R-type instruction and for sw•Now, let’s look at examples for beq and lw5Instruction Execution (reminder)•beq–Fetch instruction and add 4 to PC beq $t0,$t1,L•Assume that L is +4 instructions away–Read two source registers $t0,$t1–Sign Extend the immediate, and shift it left by 2 •0x0003 0x0000000c–Perform the test, and update the PC if it is true •If $t0 == $t1, the PC = PC + 4 + 0x0000000c6 0x10010000: beq $t0,$t1,L L == 10010010; $t0 = 4; $t1 = 40x100100040x10010004440100001001000000000110x00030001000x000000030x0000000c0x100100100x10010010041001laterXSub10X073518803232100010320x112233440x112233440x11223344(PC+4)(PC+4)(PC+4)MemReadRegWriteBranch=0RegDest=0ALUSrc=1832MemtoReg=1lw r8,32(r18)r18 = 1000; M[1032] = 0x112233448Control Signal Table Now let’s understand these,and the other ALU signals•The setting of the control lines is completely determined by the opcode field9Actual operation of ALUInput based on opcodeInput from funct field of instruction10lw,sw: add; beq: sub;R-inst: depends on funct ALUOp1 ALUOp0Funct = 0x20 for add; 0x22 for sub; 0x24 for and; etc.11ALU Control•ALU control input –000: AND–001: OR–010: ADD–110: SUB–111: SET-IF-LESS-THAN •On the diagram (next slide)12Actual operation of ALU000:and001:or010:add110:sub111:slt13ALU Control Next slide: just the truth table values14ALU Control Unit Truth Table Input to ALU control unitOutput from ALU control unit [input to ALU itself]15Output000:and001:or010:add110:sub111:sltInputs16Control Unit DesignControl UnitALU Control UnitTrace through pieces of this logic: in lecture17RegDst = 1 if opcode is000000.18ALU Control19Datapath w/ Jump20Transition to Multi-Cycle Control•So far: ideas of functional units, datapath, control. We’ll continue to use these ideas…•But so far, all instructions take a single cycle•It turns out that this is too inefficient21What We Have Now22Functional Units Used23Single-Cycle Execution Timing(in pico-seconds)24Single-Cycle Exe. Problem•The cycle time depends on the most time-consuming instruction–What happens if we implement a more complex instruction, e.g., a floating-point mult.–All resources are simultaneously active – there is no sharing of resources•Multi-cycle solution–Use a faster clock–Allow a different number of clock cycles per instruction25A Multi-cycle Datapath•A single memory unit for both instructions and data•Single ALU rather than ALU & two adders•Registers added after every major functional unit to hold the output until it is used in a subsequent clock cycle26Multi-cycle Approach•Reusing functional units–Break up instruction execution into smaller steps–We’ll need more and expanded MUX’s•At the end of a cycle, keep results in registers–So, registers are added to the datapath•Now, control signals are NOT solely determined by the instruction bits, but they also depend on which cycle it is•Controls will be generated by a finite state
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