CS/COE0447 Computer Organization & Assembly LanguageA Simple MIPSAn Abstract Implementation (fig 5.1)Instruction ExecutionInstruction Execution, cont’dSlide 6Components: Building a DatapathComponents, cont’dBuilding Blocks (figs 5.7-5.8)Instruction FetchBranch Datapath (fig. 5.9)Memory + R-Instructions (fig 5.10)Slide 13Slide 14Datapath so far (fig 5.11)Instruction FormatMore Elaborated Design (fig 5.15)A First Look at Control (fig 5.17)Control Signals OverviewGeneric Control Sequence1CS/COE0447Computer Organization & Assembly LanguageChapter 5Part 12A Simple MIPS•Memory reference instructions–lw (load word) and sw (store word)•Arithmetic-logical instructions–add, sub, and, or, and slt•Control-transfer instructions–beq (branch if equal)–j (unconditional jump)3An Abstract Implementation (fig 5.1)•Combinational logic –ALU, adder•Sequential logic–Register file, instruction memory, data memory4Instruction Execution•lw (load word)–Fetch instruction–Read a base register–Sign-extend the immediate offset–Add two values to get address–Access data memory with the address–Store the memory data to the destination register5Instruction Execution, cont’d•add–Fetch instruction–Read two source registers–Add two values–Store the result to the destination register6Instruction Execution, cont’d•j–Fetch instruction–Take the 26-bit immediate field–Shift left by 2 (to make 28-bit immediate)–Get 4 bits from the current PC and attach to the left of the immediate–Assign the value to PC7Components: Building a Datapath•ALU – Arithmetic (add,sub) and logic (and, or) Unit•Memory–Instruction memory to supply instructions–Data memory (loading and storing)•PC–Essentially a register–Update logic (increment/jump address)8Components, cont’d•Register file–32 32-bit registers–2 read ports, one write port•Immediate–Sometimes instruction contains immediate–We may sign-extend it•Support for branch and jump9Building Blocks (figs 5.7-5.8)10Instruction FetchInstruction widthis 4 bytes!Instruction memoryhere is read-only!PC keeps the currentmemory addressfrom which instructionis fetched11Branch Datapath (fig. 5.9)12Memory + R-Instructions (fig 5.10) Imm. offsetfor addressLoad datafrom memoryTo be ina register!•E.G: lw $t0,8($t1)13Memory + R-Instructions (fig 5.10) •E.G: sw $t0,8($t1)14Memory + R-Instructions (fig 5.10) •E.G: add $t0,$t1,$t2; MUX selections are reversed15Datapath so far (fig 5.11)j not consideredso far!16Instruction Format17More Elaborated Design (fig 5.15)ALU control bitsfrom I[5:0]Write register #selection18A First Look at Control (fig 5.17)19Control Signals Overview•RegDst: which instr. field to use for dst. register specifier?–instruction[20:16] vs. instruction[15:11]•ALUSrc: which one to use for ALU src 2?–immediate vs. register read port 2•MemtoReg: is it memory load?•RegWrite: update register?•MemRead: read memory?•MemWrite: write to memory?•Branch: is it a branch?•ALUop: what type of ALU operation?20Generic Control Sequence•For each fetched instruction–(decoding)–Select two registers to read from register file–Select the 2nd ALU input–Select ALU operation–Select if data memory is to be accessed–Select if register file is updated–Select what to assign to
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