CS/COE0447 Computer Organization & Assembly LanguageMulti-Cycle Execution: R-typeMulti-cycle Execution: lwMulti-cycle Execution: swMulti-cycle execution: beqMulti-cycle execution: jFig 5.28 Our final multicycle datapathA FSM State Diagram1CS/COE0447Computer Organization & Assembly LanguageChapter 5 Part 3Short reference version2Multi-Cycle Execution: R-type•Instruction fetch–IR <= Memory[PC]; sub $t0,$t1,$t2–PC <= PC + 4;•Decode instruction/register read–A <= Reg[IR[25:21]]; rs–B <= Reg[IR[20:16]]; rt–ALUOut <= PC + (sign-extend(IR[15:0])<<2);•Execution–ALUOut <= A op B; op = add, sub, and, or,…•Completion–Reg[IR[15:11]] <= ALUOut; $t0 <= ALU result3Multi-cycle Execution: lw•Instruction fetch–IR <= Memory[PC]; lw $t0,-12($t1)–PC <= PC + 4;•Instruction Decode/register read–A <= Reg[IR[25:21]]; rs–B <= Reg[IR[20:16]];–ALUOut <= PC + (sign-extend(IR[15:0])<<2);•Execution–ALUOut <= A + sign-extend(IR[15:0]); $t1 + -12 (sign extended) •Memory Access–MDR <= Memory[ALUOut]; M[$t1 + -12]•Write-back–Load: Reg[IR[20:16]] <= MDR; $t0 <= M[$t1 + -12]4Multi-cycle Execution: sw•Instruction fetch–IR <= Memory[PC]; sw $t0,-12($t1)–PC <= PC + 4;•Decode/register read–A <= Reg[IR[25:21]]; rs–B <= Reg[IR[20:16]]; rt–ALUOut <= PC + (sign-extend(IR[15:0])<<2);•Execution–ALUOut <= A + sign-extend(IR[15:0]); $t1 + -12 (sign extended) •Memory Access–Memory[ALUOut] <= B; M[$t1 + -12] <= $t05Multi-cycle execution: beq•Instruction fetch–IR <= Memory[PC]; beq $t0,$t1,label–PC <= PC + 4;•Decode/register read–A <= Reg[IR[25:21]]; rs–B <= Reg[IR[20:16]]; rt –ALUOut <= PC + (sign-extend(IR[15:0])<<2);•Execution–if (A == B) then PC <= ALUOut; •if $t0 == $t1 perform branch6Multi-cycle execution: j•Instruction fetch–IR <= Memory[PC]; j label–PC <= PC + 4;•Decode/register read–A <= Reg[IR[25:21]];–B <= Reg[IR[20:16]];–ALUOut <= PC + (sign-extend(IR[15:0])<<2);•Execution–PC <= {PC[31:28],IR[25:0],”00”};7Fig 5.28 Our final multicycle datapath8A FSM State
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