Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71CS/COE0447 Computer Organization and Assembly LanguageCS/COE0447Computer Organization & Assembly LanguageLECTURE NOTEChapter 5CS/COE0447 Computer Organization and Assembly LanguageA Simple MIPS•Memory reference instructions–lw (load word) and sw (store word)•Arithmetic-logical instructions–add, sub, and, or, and slt•Control-transfer instructions–beq (branch if equal)–j (unconditional jump)CS/COE0447 Computer Organization and Assembly LanguageImplementation Overview•Send program counter (PC) to code memory and fetch an instruction•Read one or two registers–Depending on the instruction type, we need to do different actions with the values read from the register file•Instructions of a same type (e.g., memory) perform similar workCS/COE0447 Computer Organization and Assembly LanguageAn Abstract Implementation•Combinational logic–ALU, adder•Sequential logic–Register file, instruction memory, data memoryCS/COE0447 Computer Organization and Assembly LanguageInstruction Analysis•lw (load word)–Fetch instruction–Read a base register–Sign-extend the immediate offset–Add two values to get address–Access data memory with the address–Store the memory data to the destination registerCS/COE0447 Computer Organization and Assembly LanguageInstruction Analysis, cont’d•add–Fetch instruction–Read two source registers–Add two values–Store the result to the destination registerCS/COE0447 Computer Organization and Assembly LanguageInstruction Analysis, cont’d•j–Fetch instruction–Take the 26-bit immediate field–Shift left by 2 (to make 28-bit immediate)–Get 4 bits from the current PC and attach to the left of the immediate–Assign the value to PC•What about other instructions?CS/COE0447 Computer Organization and Assembly LanguageComponents•ALU–We’ve already built this!•Memory–Instruction memory to supply instructions–Data memory to supply data–Data memory allows writing to it (store)•PC–Essentially a register–Update logic (increment/jump address)CS/COE0447 Computer Organization and Assembly LanguageComponents, cont’d•Register file–32 32-bit registers–2 read ports, one write port•Immediate–Sometimes instruction contains immediate–We may sign-extend it•Support for branch and jumpCS/COE0447 Computer Organization and Assembly LanguageBuilding BlocksCS/COE0447 Computer Organization and Assembly LanguageInstruction FetchInstruction widthis 4 bytes!Instruction memoryhere is read-only!PC keeps the currentmemory addressfrom which instructionis fetchedCS/COE0447 Computer Organization and Assembly LanguageOperand FetchFor branches!Two readsat a time!CS/COE0447 Computer Organization and Assembly LanguageHandling Memory InstructionsImm. offsetfor addressData to store!Load datafrom memoryTo be ina register!CS/COE0447 Computer Organization and Assembly LanguageDatapath so farj instructionnot consideredso far!CS/COE0447 Computer Organization and Assembly LanguageInstruction FormatCS/COE0447 Computer Organization and Assembly LanguageMore Elaborated DesignALU control bitsfrom I[5:0]Write register #selectionCS/COE0447 Computer Organization and Assembly LanguageA First Look at ControlCS/COE0447 Computer Organization and Assembly LanguageControl Signals Overview•RegDst: which instr. field to use for dst. register specifier?–instruction[20:16] vs. instruction[15:11]•ALUSrc: which one to use for ALU src 2?–immediate vs. register read port 2•MemtoReg: is it memory load?•RegWrite: update register?•MemRead: read memory?•MemWrite: write to memory?•Branch: is it a branch?•ALUop: what type of ALU operation?CS/COE0447 Computer Organization and Assembly LanguageGeneric Control Sequence•For each fetched instruction–(decoding)–Select two registers to read from register file–Select the 2nd register input–Select ALU operation–Select if data memory is to be accessed–Select if register file is updated–Select what to assign to PCCS/COE0447 Computer Organization and Assembly LanguageExample: lw r8, 32(r18)•Let’s assume r18 has 1,000•Let’s assume M[1032] has 0x11223344I-FormatCS/COE0447 Computer Organization and Assembly LanguageExample: lw r8, 32(r18)3518803232100010320x112233440x112233440x11223344(PC+4)(PC+4)(PC+4)MemReadRegWriteBranch=0RegDest=0ALUSrc=1832MemtoReg=1CS/COE0447 Computer Organization and Assembly LanguageControl Sequence for lw•OPcode = 35–RegDst = 0–ALUSrc = 1–MemtoReg = 1–RegWrite = 1–MemRead = 1–MemWrite = 0–Branch = 0–ALUop = 0CS/COE0447 Computer Organization and Assembly LanguageControl Signal TableCS/COE0447 Computer Organization and Assembly LanguageALU Control•Depending on instruction, we perform different ALU operation•Example–lw or sw: ADD–and: AND–beq: SUB•ALU control input (3 bits)–000: AND–001: OR–010: ADD–110: SUB–111: SET-IF-LESS-THAN (similar to SUB)CS/COE0447 Computer Organization and Assembly LanguageALU Control, cont’d•ALUop–00: lw/sw, 01: beq, 10: arithmetic, 11: jumpCS/COE0447 Computer Organization and Assembly LanguageALU Control Truth TableCS/COE0447 Computer Organization and Assembly LanguageALU Control Logic DesignCS/COE0447 Computer Organization and Assembly LanguageDatapath w/ JumpCS/COE0447 Computer Organization and Assembly LanguageFunctional Unit UsedCS/COE0447 Computer Organization and Assembly LanguageRegister File ImplementationCS/COE0447 Computer Organization and Assembly LanguageReg. File Impl., cont’d110x112233440x11223344000CS/COE0447 Computer Organization and Assembly LanguageWhat We Have NowCS/COE0447 Computer Organization and Assembly LanguageResource UsageCS/COE0447 Computer Organization and Assembly LanguageSingle-Cycle Execution Timing(in pico-seconds)CS/COE0447 Computer Organization and Assembly LanguageSingle-Cycle Exe. Problem•The cycle time depends on the most time-consuming instruction–What happens if we implement a more complex